{"id":4045540,"url":"https://alion.io/job/cadence-design-systems-lead-design-engineer-26","title":"lead Design Engineer","company":{"id":4351,"name":"Cadence Design Systems","domain":"cadence.com","url":"https://alion.io/company/cadence","size_band":"5000+","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Workday","truth_index":{"grade":"B","score":81,"open_postings":109,"ghost_share":0,"stale_share":0.78,"repost_share":0,"time_to_fill_p50_days":58,"computed_at":"2026-11-12T10:38:37Z"}},"role":"Industrial Engineering","role_family":"Industrial Engineering","seniority":"lead","employment_type":"full_time","work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Hyderabad, India"],"countries":["IN"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":null,"experience_years_min":2,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"Ansys RedHawk","optional":false},{"name":"HPC","optional":false},{"name":"Perl","optional":false},{"name":"Python","optional":false},{"name":"Synopsys Custom Compiler","optional":false},{"name":"Synopsys HSPICE","optional":false}],"status":"live","first_seen_at":"2026-11-10T23:46:00Z","employer_posted_date":"2026-11-10","last_verified_at":"2026-11-12T13:51:21Z","board_verified":true,"closed_at":null,"days_open":1,"trust":{"level":"ok","repost_count":null,"flags":[],"days_open":1},"description":"At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.\nCircuit Pathfinding Engineer\nThe Technology Pathfinding team within the Silicon Solutions Group ensures that our analog mixed-signal (AMS) IP products take maximum advantage of process technology offerings and roadmap from foundries. To do this, we have expertise in technology analysis, design technology co-optimization (DTCO), circuit design and optimization. AI and HPC products demand increasing compute power, higher memory bandwidth and faster chip to chip communication. We work with foundries and our IP design teams to chart the path that gets us there. Join us if you enjoy working with cutting-edge technology nodes (2nm and lower), designing high-speed analog circuits, and hunting down optimizations that improve performance, power and area (PPA).\nRole:\nCircuit design of key AMS circuits to benchmark and optimize PPA in an early stage/experimental technology setting\nAnalyze complex PPA trade-offs related to timing, power, area and reliability\nEvaluate advanced process development kits (PDKs) from a design and competitiveness viewpoint\nConduct DTCO on technology features and foundation IP to maximize PPA \nRequirements:\nBachelors degree in Science/Engineering with 2-5 years of industry experience OR Masters degree in Science/Engineering with 1-4 years of industry experience\nIndustry experience in analog circuit design and layout, preferably on advanced technology nodes\nAcademic coursework on analog design from a reputed university covering CMOS/GAA fundamentals, device-technology interaction such as layout dependent effects and factors affecting circuit PPA\nFamiliarity with industry tools for analog and custom design such as simulation tools (Spectre, Hspice), custom design (Virtuoso, Custom Compiler), and reliability (Voltus, Redhawk)\nProgramming skills in a scripting language like Python, TCL, Perl, etc. Experience in using and building AI agentic flows is a plus.\nWe’re doing work that matters. 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