{"id":294156,"url":"https://alion.io/job/cadence-design-systems-lead-design-engineer-3","title":"Lead Design Engineer","company":{"id":4351,"name":"Cadence Design Systems","domain":"cadence.com","url":"https://alion.io/company/cadence","size_band":"5000+","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Workday","truth_index":{"grade":"B","score":82,"open_postings":112,"ghost_share":0,"stale_share":0.723,"repost_share":0,"time_to_fill_p50_days":57,"computed_at":"2026-10-29T05:49:05Z"}},"role":"Hardware","role_family":"Hardware","seniority":"lead","employment_type":"full_time","work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Hyderabad, India"],"countries":["IN"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":{"min_usd":28000,"max_usd":64000,"period":"year","method":"global_role_cell_scaled_by_country","sample_n":796},"experience_years_min":10,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"Perl","optional":false},{"name":"Python","optional":false},{"name":"SystemVerilog","optional":false},{"name":"Verilog","optional":false},{"name":"Formal Verification","optional":true}],"status":"live","first_seen_at":"2026-08-26T00:00:00Z","employer_posted_date":"2026-08-26","last_verified_at":"2026-10-29T11:04:15Z","board_verified":true,"closed_at":null,"days_open":64,"trust":{"level":"ok","repost_count":null,"flags":[],"days_open":64},"description":"At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.\nJob Profile\nRole Title\nLead Design Engineer, SoC / Subsystem / IP Design\nExperience\n4to 18 years\nQualification:BE/BTECH/ME/MTECH\nRole Summary\nLead the design and integration of complex SoC, subsystem, and IP blocks from architecture interpretation through RTL delivery and design closure. Own micro-architecture, RTL development, quality reviews, and cross-functional coordination with verification, physical design, DFT, firmware, and architecture teams. Drive high-quality, reusable, and implementation-ready designs aligned to power, performance, and area targets.\nKey Responsibilities\nOwn end-to-end RTL design and development of SoC, subsystem, and IP blocks. Translate architecture and product requirements into detailed micro-architecture and implementation plans. Develop high-quality RTL in Verilog/SystemVerilog with focus on correctness, reusability, and scalability. Lead design of key blocks such as interconnects, controllers, bridges, memory interfaces, datapaths, and control logic. Drive block-level and subsystem-level design integration and resolve interface, timing, and functionality issues. Work closely with verification teams to review test plans, support debug, and ensure design quality and closure. Collaborate with physical design teams on timing, power, area, clocking, reset, and synthesis constraints. Support DFT, CDC, RDC, lint, low-power, and formal checks, and drive closure on design issues. Review specifications, micro-architecture documents, RTL, and design changes to ensure robustness and quality. Analyze and resolve design bugs found in simulation, emulation, silicon bring-up, or customer use cases. Mentor junior engineers and provide technical direction on coding practices, design quality, and methodology. Contribute to design methodology improvements, reusable IP development, and automation initiatives.\nRequired Skills and Qualifications\nBachelor’s or Master’s degree in Electronics, Electrical Engineering, Computer Engineering, or related field. 10 to 14 years of experience in digital design with strong exposure to IP, subsystem, and SoC development. Strong expertise in RTL design using Verilog/SystemVerilog. Solid understanding of digital design fundamentals, FSMs, pipelines, arbitration, buffering, and clock/reset design. Strong experience in micro-architecture definition and hardware implementation. Good understanding of AMBA protocols such as AXI, AHB, and APB. Experience in designing interconnects, bus fabrics, DMA, memory-mapped peripherals, control/data path logic, or protocol bridges. Strong debugging skills for simulation, synthesis, and integration issues. Familiarity with lint, CDC, RDC, synthesis, STA constraints, DFT, and low-power design flows. Exposure to power, performance, and area optimization techniques. Scripting experience in Python, Perl, Tcl, or Shell for automation and productivity improvements. Strong communication and cross-functional collaboration skills.\nPreferred Skills\nExperience with PCIe, DDR, NoC, cache/coherency, security, or safety-related designs. Exposure to low-power design methodologies including UPF/CPF. Experience with formal verification support and silicon debug. Experience leading small design teams or owning major subsystems in large SoC programs.\nKey Competencies\nRTL and micro-architecture ownership SoC and subsystem integration Technical leadership Problem solving and debug Quality and design closure focus\nWe’re doing work that matters. Help us solve what others can’t.","description_format":"text","description_chars":3607,"description_truncated":false,"requirements":{"experience_years_min":10,"management_years_min":null,"team_size_min":null,"manages_managers":false,"education":{"level":"bachelor","optional":false},"security_clearance":false,"languages":[]},"benefits":[],"hiring_locations":[],"hiring_excludes":[],"relocation_offered":false,"industries":["EDA Software","Semiconductor IP & Chip Design Services"],"lifecycle":[{"event":"open","at":"2026-09-05T14:34:45Z"}],"visa":[],"liveness":{"score":20,"band":"cold","label":"Long shot","p_open":1,"p_active":0.372,"p_room":0.55,"age_days":64,"expected_fill_days":57,"reasons":["conf:10","stale_co","evergreen","wave","velocity","win:tail","comp:brand"],"computed_at":"2026-10-29T05:49:05Z"},"pay":null,"html_url":"https://alion.io/job/cadence-design-systems-lead-design-engineer-3","json_url":"https://alion.io/job/cadence-design-systems-lead-design-engineer-3.json","meta":{"generated_at":"2026-10-29T16:35:17Z","cache_seconds":300,"methodology":"https://alion.io/methodology","terms":"https://alion.io/terms","contact":"https://alion.io/contact","api":"https://alion.io/developers","about":"Alion is a live layer of people, companies and AI agents: who they are, whether they are real and active right now, what they do and how to work with them, readable by people and by agents and paid per call.","catalog":"https://alion.io/catalog.json","usage":{"tier":"crawler_verified","counted_by":"address","units_charged":1,"used_today":24704,"day_limit":null,"remaining_today":null,"minute_limit":300,"resets_at":"2026-10-30T00:00:00Z"}},"offers":[{"id":"company.slices","title":"One company in depth, by slice","status":"live","price":{"credits":0.02,"usd":0.002,"plus_per_slice":{"credits":0.05,"usd":0.005}},"unit":"per company, plus each slice with data","note":"the employer in depth","call":{"mcp_tool":"get_company","arguments":{"id":4351},"rest":"https://alion.io/mcp/rest/get_company?id=4351"},"human":"https://alion.io/catalog?offer=company.slices&for=job%2Fcadence-design-systems-lead-design-engineer-3"},{"id":"market.stats","title":"A market slice: pay, demand and time to fill","status":"live","price":{"credits":1,"usd":0.1},"unit":"per slice","note":"pay, demand and time to fill for this role and place","call":{"mcp_tool":"market_stats"},"human":"https://alion.io/catalog?offer=market.stats&for=job%2Fcadence-design-systems-lead-design-engineer-3"},{"id":"job.search","title":"Open jobs by role, technology, place, pay and visa","status":"live","price":{"credits":0.02,"usd":0.002},"unit":"per posting in a list","note":"similar open postings","call":{"mcp_tool":"search_jobs"},"human":"https://alion.io/catalog?offer=job.search&for=job%2Fcadence-design-systems-lead-design-engineer-3"},{"id":"company.verify","title":"Is this company real and active right now","status":"pilot","price":null,"unit":"per company","request":{"url":"https://alion.io/catalog/request","method":"POST","body":"{\"offer\": \"company.verify\", \"for\": \"job/cadence-design-systems-lead-design-engineer-3\", \"note\": \"what you need it for\"}"},"human":"https://alion.io/catalog?offer=company.verify&for=job%2Fcadence-design-systems-lead-design-engineer-3"}],"agent":{"mcp":"https://alion.io/mcp/jobs","mcp_open":"https://alion.io/mcp/open","next":[{"tool":"get_job","arguments":{"id":294156}},{"tool":"search_jobs","arguments":{"company":"cadence.com","detail":"compact"}},{"tool":"match_people","arguments":{"job_id":294156},"note":"people open to offers who fit this vacancy"}],"note":"The same data through MCP tools: https://alion.io/mcp/open needs no sign-in (compact searches, postings, people); https://alion.io/mcp with an Alion account has everything. Docs: https://alion.io/developers"}}