{"id":792218,"url":"https://alion.io/job/cadence-design-systems-lead-design-engineer-8","title":"Lead Design Engineer","company":{"id":4351,"name":"Cadence Design Systems","domain":"cadence.com","url":"https://alion.io/company/cadence","size_band":"5000+","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Workday","truth_index":{"grade":"B","score":82,"open_postings":112,"ghost_share":0,"stale_share":0.723,"repost_share":0,"time_to_fill_p50_days":57,"computed_at":"2026-10-29T05:49:05Z"}},"role":"Hardware","role_family":"Hardware","seniority":"lead","employment_type":"full_time","work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"explicit","locations":["Nanjing, China"],"countries":["CN"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":{"min_usd":50000,"max_usd":113000,"period":"year","method":"global_role_cell_scaled_by_country","sample_n":796},"experience_years_min":5,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"C++","optional":false},{"name":"Cadence Palladium","optional":false},{"name":"Python","optional":false},{"name":"SystemVerilog","optional":false}],"status":"live","first_seen_at":"2026-09-12T03:46:13Z","employer_posted_date":"2026-09-29","last_verified_at":"2026-10-29T06:01:47Z","board_verified":true,"closed_at":null,"days_open":47,"trust":{"level":"ok","repost_count":null,"flags":[],"days_open":47},"description":"At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.\nJob Title: Lead Design Engineer\nLocation: Nanjing, China\nCadence is a pivotal leader in electronic design, building upon more than 30 years of computational software expertise. The company applies its underlying Intelligent System Design strategy to deliver software, hardware and IP that turn design concepts into reality. Cadence customers are the world’s most innovative companies, delivering extraordinary electronic products from chips to boards to systems for the most dynamic market applications including consumer, hyperscale computing, 5G communications, automotive, aerospace industrial and health.\nThe Cadence Advantage\nThe opportunity to work on cutting-edge technology in an environment that encourages you to be creative, innovative, and to make an impact.\nCadence’s employee-friendly policies focus on the physical and mental well-being of employees, career development, providing opportunities for learning, and celebrating success in recognition of specific needs of the employees.\nThe unique “One Cadence - One Team” culture promotes collaboration within and across teams to ensure customer success.\nMultiple avenues of learning and development available for employees to explore as per their specific requirement and interests.\nYou get to work with a diverse team of passionate, dedicated, and talented individuals who go above and beyond for our customers, our communities, and each other-every day.\nJob Summary:\nSenior Frontend Design Engineer for Advanced Physical IP Development.\nJoin a growing and dynamic organization developing and leading the proliferation of best-in-class physical IP for industry-standard protocols. This is a tremendous opportunity to work with an experienced and full skillset team focusing on high-performance IP AND to engage with technology sector’s top companies making an impact in our world.\nThe role will be a highly motivated technical expert who is able to work independently and collaboratively complete IP projects within required timelines and deliverables with high quality. The candidate will contribute to overall specification definition, industry standard workgroup, digital architecture, digital RTL, low power design, etc., as well as partnering with Project Manager collaborating with digital verification, analog, layout, backend design, lab validation teams in Nanjing and multiple worldwide geographies, and pre/post-silicon application support for global customers. The candidate should possess strong communication skills in both English and Mandarin with ability to manage multiple tasks and priorities on day-to-day basis.\nPrimary Responsibilities:\nKey contributor and senior technical engineer in the IP frontend design team, especially on high-performance Consumer PHYs including eUSB2v2, USB4-PHY, PCIe, ONFI, eDP/DP, SATA, etc.\nDrive architecture to micro-architecture to RTL implementation with the refining of features/requirements throughout the design process\nUnderstanding of synthesis, constraint generation, power management and DFT\nUnderstanding of low-power designs and features (power islands, state retention, isolation, etc.)\nWork with digital verification team to specify coverage points, testing strategy, corner conditions, stimulus creation and FPGA/Palladium testing\nPartner closely with Project Management Office to collaborate with various skill groups in Nanjing and multiple worldwide geographies to complete the IP deliverables with high quality, including Analog, Layout, Backend, Firmware, Lab Bring-up/Validation, Pre/Post-Silicon Product Engineering\nWork with wider engineering and IP delivery/release teams to develop and use infrastructure to integrate IPs into subsystems and QA for customer releases\nPosition Requirements:\nMS / BS in Electrical/Computer Engineering or related degree.\n5+ years of relative industry working experience.\n3+ years of experience in ASIC design role for delivering advanced IP and/or ASIC/SOC products.\nDeep knowledge of best practices and flows in Design Architecture, RTL design/verification and ASIC end-to-end methodology.\nKnowledge of one or more industry serial standards, such as USB, DP, PCIe, Ethernet, etc.\nUnderstanding basics of Analog Mixed-Signal, SI/PI, Post-Silicon Validation, and system view of physical interface IPs and their typical applications.\nOne Team mentality with a passion to innovate and can-do attitude.\nStrong cross-functional communication skills in both English and Mandarin.\nSelf-starter and highly motivated.\nQualifications as Plus\nDirect experience of high-speed serial interface link IPs in advanced technology nodes.\nKnowledge of multiple programming languages, System Verilog, Python, C/C++, etc.\nKnowledge of embedded microcontroller or DSP usage and FW.\nExperience with various Cadence ASIC design tools.\nWe’re doing work that matters. Help us solve what others can’t.","description_format":"text","description_chars":4957,"description_truncated":false,"requirements":{"experience_years_min":5,"management_years_min":null,"team_size_min":null,"manages_managers":false,"education":{"level":"bachelor","optional":false},"security_clearance":false,"languages":[{"language":"English","level":"All levels","optional":false}]},"benefits":[],"hiring_locations":[{"name":"China","iso":"CN","kind":"country"}],"hiring_excludes":[],"relocation_offered":false,"industries":["EDA Software","Semiconductor IP & Chip Design Services"],"lifecycle":[{"event":"open","at":"2026-09-12T03:46:13Z"}],"visa":[],"liveness":{"score":29,"band":"fade","label":"Fading","p_open":1,"p_active":0.387,"p_room":0.75,"age_days":47,"expected_fill_days":57,"reasons":["conf:10","stale_co","evergreen","wave","velocity","win:late","comp:brand"],"computed_at":"2026-10-29T05:49:05Z"},"pay":null,"html_url":"https://alion.io/job/cadence-design-systems-lead-design-engineer-8","json_url":"https://alion.io/job/cadence-design-systems-lead-design-engineer-8.json","meta":{"generated_at":"2026-10-29T09:36:27Z","cache_seconds":300,"methodology":"https://alion.io/methodology","terms":"https://alion.io/terms","contact":"https://alion.io/contact","api":"https://alion.io/developers","about":"Alion is a live layer of people, companies and AI agents: who they are, whether they are real and active right now, what they do and how to work with them, readable by people and by agents and paid per call.","catalog":"https://alion.io/catalog.json","usage":{"tier":"crawler_verified","counted_by":"address","units_charged":1,"used_today":14542,"day_limit":null,"remaining_today":null,"minute_limit":300,"resets_at":"2026-10-30T00:00:00Z"}},"offers":[{"id":"company.slices","title":"One company in depth, by slice","status":"live","price":{"credits":0.02,"usd":0.002,"plus_per_slice":{"credits":0.05,"usd":0.005}},"unit":"per company, plus each slice with data","note":"the employer in depth","call":{"mcp_tool":"get_company","arguments":{"id":4351},"rest":"https://alion.io/mcp/rest/get_company?id=4351"},"human":"https://alion.io/catalog?offer=company.slices&for=job%2Fcadence-design-systems-lead-design-engineer-8"},{"id":"market.stats","title":"A market slice: pay, demand and time to fill","status":"live","price":{"credits":1,"usd":0.1},"unit":"per slice","note":"pay, demand and time to fill for this role and place","call":{"mcp_tool":"market_stats"},"human":"https://alion.io/catalog?offer=market.stats&for=job%2Fcadence-design-systems-lead-design-engineer-8"},{"id":"job.search","title":"Open jobs by role, technology, place, pay and visa","status":"live","price":{"credits":0.02,"usd":0.002},"unit":"per posting in a list","note":"similar open postings","call":{"mcp_tool":"search_jobs"},"human":"https://alion.io/catalog?offer=job.search&for=job%2Fcadence-design-systems-lead-design-engineer-8"},{"id":"company.verify","title":"Is this company real and active right now","status":"pilot","price":null,"unit":"per company","request":{"url":"https://alion.io/catalog/request","method":"POST","body":"{\"offer\": \"company.verify\", \"for\": \"job/cadence-design-systems-lead-design-engineer-8\", \"note\": \"what you need it for\"}"},"human":"https://alion.io/catalog?offer=company.verify&for=job%2Fcadence-design-systems-lead-design-engineer-8"}],"agent":{"mcp":"https://alion.io/mcp/jobs","mcp_open":"https://alion.io/mcp/open","next":[{"tool":"get_job","arguments":{"id":792218}},{"tool":"search_jobs","arguments":{"company":"cadence.com","detail":"compact"}},{"tool":"match_people","arguments":{"job_id":792218},"note":"people open to offers who fit this vacancy"}],"note":"The same data through MCP tools: https://alion.io/mcp/open needs no sign-in (compact searches, postings, people); https://alion.io/mcp with an Alion account has everything. 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