{"id":1442924,"url":"https://alion.io/job/cadence-design-systems-lead-design-engineer-verification","title":"Lead Design Engineer - Verification","company":{"id":4351,"name":"Cadence Design Systems","domain":"cadence.com","url":"https://alion.io/company/cadence","size_band":"5000+","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Workday","truth_index":{"grade":"B","score":81,"open_postings":110,"ghost_share":0,"stale_share":0.745,"repost_share":0,"time_to_fill_p50_days":57,"computed_at":"2026-10-24T06:02:35Z"}},"role":"Hardware","role_family":"Hardware","seniority":"lead","employment_type":"full_time","work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Nanjing, China"],"countries":["CN"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":{"min_usd":50000,"max_usd":115000,"period":"year","method":"global_role_cell_scaled_by_country","sample_n":741},"experience_years_min":3,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"Cadence JasperGold","optional":false},{"name":"Cadence Palladium","optional":false},{"name":"Cadence vManager","optional":false},{"name":"Cadence Xcelium","optional":false},{"name":"Perl","optional":false},{"name":"Python","optional":false},{"name":"SystemVerilog","optional":false},{"name":"UVM","optional":false}],"status":"live","first_seen_at":"2026-09-29T05:28:22Z","employer_posted_date":"2026-09-29","last_verified_at":"2026-10-22T06:53:03Z","board_verified":false,"closed_at":null,"days_open":25,"trust":{"level":"ok","repost_count":null,"flags":[],"days_open":25},"description":"At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.\nPrimary Responsibilities:\n- Contributor and senior technical engineer in the IP verification team, especially on high-performance Consumer PHYs including eUSB2v2, USB4-PHY, PCIe, eDP/DP, SATA, etc.\n- Develop and maintain UVM-based verification environments: testbench architecture, agents/UVCs, sequences, scoreboards, register models (UVM RAL) and checkers, from block level to PHY top and controller+PHY subsystem level.\n- Create verification plans (vPlan) from protocol specifications and design documents; define functional coverage models, assertions (SVA) and testing strategy including corner conditions and error injection; drive coverage closure and signoff quality metrics.\n- Run and maintain regressions with simulation/regression platforms (Xcelium, vManager); triage failures, debug RTL/testbench issues with waveform tools (Verisium/SimVision), and track them to root cause and closure.\n- Apply low-power verification (power islands, state retention, isolation), clock/reset domain crossing checks (CDC/RDC), X-propagation, gate-level simulation and formal techniques as required by the project.\n- Integrate and configure commercial VIPs for serial protocols; verify firmware/hardware interaction and PHY bring-up/configuration flows together with firmware and design teams.\n- Work with the design team on testability of features, support lab bring-up and pre/post-silicon debug for global customers.\n- Partner closely with the Project Management Team to collaborate with various skill groups in Nanjing and multiple worldwide geographies to complete the IP deliverables with high quality; contribute to verification infrastructure, methodology and QA for customer releases.\nPosition Requirements:\n- MS / BS in Electrical/Computer Engineering or related degree.\n- 3+ years of relative industry working experience in digital/ASIC verification.\n- Solid hands-on experience with SystemVerilog and UVM; good knowledge of best practices and flows in constrained-random verification, functional coverage and assertion-based verification within an end-to-end methodology.\n- Knowledge of one or more industry serial standards, such as USB, DP, PCIe, Ethernet, etc., and their link training / power management / protocol layering.\n- Experience with verification planning and coverage-driven signoff.\n- Understanding basics of Analog Mixed-Signal verification, and a system view of physical interface IPs and their typical applications.\n- One Team mentality with a passion to innovate and a can-do attitude.\n- Strong cross-functional communication skills in both English and Mandarin.\n- Self-starter and highly motivated.\nQualifications as Plus\n- Direct verification experience of high-speed serial interface link IPs (PHY/PCS/controller) in advanced technology nodes.\n- Experience with Cadence verification tool suite: Xcelium, vManager, Verisium, JasperGold (formal/CDC), Palladium emulation.\n- Experience with low-power verification (UPF/CPF), gate-level simulation, and mixed-signal co-simulation.\n- Scripting and automation skills: Python, Perl, Tcl, Makefile/regression infrastructure; interest in AI-assisted verification\n- Experience controller+PHY subsystem-level verification.\nWe’re doing work that matters. Help us solve what others can’t.","description_format":"text","description_chars":3364,"description_truncated":false,"requirements":{"experience_years_min":3,"management_years_min":null,"team_size_min":null,"manages_managers":false,"education":{"level":"bachelor","optional":false},"security_clearance":false,"languages":[{"language":"English","level":"All levels","optional":false}]},"benefits":[],"hiring_locations":[],"hiring_excludes":[],"relocation_offered":false,"industries":["EDA Software","Semiconductor IP & Chip Design Services"],"lifecycle":[{"event":"open","at":"2026-09-29T05:28:22Z"}],"visa":[],"liveness":{"score":54,"band":"ok","label":"Likely open","p_open":1,"p_active":0.605,"p_room":0.9,"age_days":25,"expected_fill_days":57,"reasons":["conf:47","stale_co","velocity","win:mid","comp:brand"],"computed_at":"2026-10-24T06:02:35Z"},"pay":null,"html_url":"https://alion.io/job/cadence-design-systems-lead-design-engineer-verification","json_url":"https://alion.io/job/cadence-design-systems-lead-design-engineer-verification.json","meta":{"generated_at":"2026-10-24T12:28:06Z","cache_seconds":300,"methodology":"https://alion.io/methodology","terms":"https://alion.io/terms","contact":"https://alion.io/contact","api":"https://alion.io/developers","about":"Alion is a live layer of people, companies and AI agents: who they are, whether they are real and active right now, what they do and how to work with them, readable by people and by agents and paid per call.","catalog":"https://alion.io/catalog.json","usage":{"tier":"crawler_verified","counted_by":"address","units_charged":1,"used_today":17880,"day_limit":null,"remaining_today":null,"minute_limit":300,"resets_at":"2026-10-25T00:00:00Z"}},"offers":[{"id":"company.slices","title":"One company in depth, by slice","status":"live","price":{"credits":0.02,"usd":0.002,"plus_per_slice":{"credits":0.05,"usd":0.005}},"unit":"per company, plus each slice with data","note":"the employer in depth","call":{"mcp_tool":"get_company","arguments":{"id":4351},"rest":"https://alion.io/mcp/rest/get_company?id=4351"},"human":"https://alion.io/catalog?offer=company.slices&for=job%2Fcadence-design-systems-lead-design-engineer-verification"},{"id":"market.stats","title":"A market slice: pay, demand and time to fill","status":"live","price":{"credits":1,"usd":0.1},"unit":"per slice","note":"pay, demand and time to fill for this role and place","call":{"mcp_tool":"market_stats"},"human":"https://alion.io/catalog?offer=market.stats&for=job%2Fcadence-design-systems-lead-design-engineer-verification"},{"id":"job.search","title":"Open jobs by role, technology, place, pay and visa","status":"live","price":{"credits":0.02,"usd":0.002},"unit":"per posting in a list","note":"similar open postings","call":{"mcp_tool":"search_jobs"},"human":"https://alion.io/catalog?offer=job.search&for=job%2Fcadence-design-systems-lead-design-engineer-verification"},{"id":"company.verify","title":"Is this company real and active right now","status":"pilot","price":null,"unit":"per company","request":{"url":"https://alion.io/catalog/request","method":"POST","body":"{\"offer\": \"company.verify\", \"for\": \"job/cadence-design-systems-lead-design-engineer-verification\", \"note\": \"what you need it for\"}"},"human":"https://alion.io/catalog?offer=company.verify&for=job%2Fcadence-design-systems-lead-design-engineer-verification"}]}