{"id":3724883,"url":"https://alion.io/job/cadence-design-systems-lead-digital-verification-engineer","title":"Lead Digital Verification Engineer","company":{"id":4351,"name":"Cadence Design Systems","domain":"cadence.com","url":"https://alion.io/company/cadence","size_band":"5000+","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Workday","truth_index":{"grade":"B","score":76,"open_postings":108,"ghost_share":0,"stale_share":0.759,"repost_share":0,"time_to_fill_p50_days":60,"computed_at":"2026-11-06T05:58:05Z"}},"role":"Hardware","role_family":"Hardware","seniority":"lead","employment_type":"full_time","work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Montreal, Canada"],"countries":["CA"],"hiring_countries":[],"hiring_countries_total":0,"salary":{"min":89600,"max":166400,"currency":"CAD","period":"year","gross":null,"usd_annual":118904},"salary_estimate":null,"experience_years_min":null,"visa_sponsorship":false,"relocation_package":false,"has_equity":true,"technologies":[{"name":"SystemVerilog","optional":false},{"name":"Formal Verification","optional":true},{"name":"Perl","optional":true},{"name":"Python","optional":true},{"name":"Ruby","optional":true},{"name":"UVM","optional":true}],"status":"live","first_seen_at":"2026-11-03T00:00:00Z","employer_posted_date":"2026-11-03","last_verified_at":"2026-11-06T08:11:43Z","board_verified":true,"closed_at":null,"days_open":3,"trust":{"level":"ok","repost_count":null,"flags":[],"days_open":3},"description":"At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.\nThis role is for an existing vacancy.\nJob Title: Lead Verification Engineer\nLocation: Montreal, Ottawa, Toronto\nOverview\nThis is an opportunity to join a dynamic and growing team of experienced engineers developing high-performance physical IP for industry-standard protocols.\nThe successful candidate will be a highly motivated self-starter who is able to work independently to complete assigned tasks within required project timelines with high quality.\nThe candidate will primarily be responsible for the verification of digital RTL and development of re-usable verification components and environments.\nIt is also expected that the candidate will contribute to all aspects of digital verification including flow development, test plan development and execution, functional coverage closure, and code coverage closure.\nThe ideal candidate will have a fundamental understanding of the end-to-end verification flow in order to accurately and efficiently communicate with all members of the technical staff regarding overall project development progress and status.\nThe most successful candidates will be able to demonstrate excellent command of fundamental logic principles as well as excellent problem solving and communication skills.\nThe candidate should be able to work as part of a small and focused team of engineers and be able to collaborate successfully as needed with design teams, verification teams, project management, and digital and analog design teams in multiple worldwide geographies.\nThe Candidate should be willing to work full time in the Montreal, Quebec, Canada office and be willing to travel as required by job function (expectation is 5% travel or less).\nDesign IP is growing organization within Cadence and our complete IP portfolio can be found here http://ip.cadence.com/ipportfolio/ip-portfolio-overview.\nMinimum Experience:\nBachelor of Science in Electrical(EE)/Computer Engineering (CPE) or Computer Science (CSC)\nUnderstanding of verification architecture and methodologies\nUnderstanding of Metric Driven Verification\nUnderstanding of Universal Verification Methodologies\nUnderstanding of the identification, planning and creation of functional coverage and checks\nUnderstanding of System Verilog Assertions (SVAs)\nUnderstanding of digital design flow\nPreferred Experience:\nMaster of Science in EE/CPE/CSC \nExperience with SystemVerilog UVM coding language is desired\nExperience with scripting languages such as Python, Perl, Ruby, Sed, or Awk is also strongly preferred\nExposure to Standard Protocol knowledge for any of the following areas: PCIe, USB, SATA, Ethernet, Display Port, HDMI\nExposure to Formal Verification Technologies\nExposure to Mixed Signal Design experience\nExperience with Cadence tools experience\nExposure to Low Power verification experience using CPF or UPF\nCadence is an equal-opportunity employer committed to hiring a diverse workforce.\nTitre: Concepteur en Vérification Numérique\nLocalisation: Montreal, Ottawa, Toronto\nDescription :\nCadence Design Systems est à la recherche de candidats d’excellence pour joindre une équipe expérimentée et dynamique d’ingénieurs en charge du développement d’IP au service des standards de l’industrie.\nLe candidat sélectionné aura la charge de la vérification de modules numériques RTL et du développement de modules de vérification réutilisables. Le candidat sera aussi amené à contribuer à toutes les phases du processus de vérification : élaboration du plan de vérification, codage des points de couverture, génération de stimuli et analyse de couverture.\nLe candidat devra posséder des connaissances de base des méthodes de design et de vérification des composantes numériques.\nLe candidat devra être autonome, dynamique et démontrer de très bonnes qualités de communication.\nLe groupe de design IP est une équipe multidisciplinaire composée d’ingénieurs provenant de divers sites à travers le monde.\nFaisant parti du groupe de vérification, le candidat sera amené à collaborer avec diverses disciplines et phases de la réalisation complète d’IP matériel : design numérique et analogique, design physique, production, etc.\nLe groupe de design IP est une organisation grandissante. Le catalogue complet se trouve au site suivant : http://ip.cadence.com/ipportfolio/ip-portfolio-overview.\nExpérience minimum:\nBaccalauréat en Ingénierie électrique, sciences appliquées ou domaine connexe.\nCompréhension des principes de base de la vérification de composantes numériques.\nCompréhension de base de la vérification basées sur les métriques (Metric Driven Verification).\nConnaissance des Méthodes de Vérification Universelles (UVM).\nConnaissance du langage d’assertions SystemVerilog (SVAs).\nCompréhension de base du flot de design numérique.\nCapable de communiquer en anglais.\nExpérience recherchée:\nMaîtrise en génie électrique, sciences appliquées ou domaine connexe.\nExpérience avec le langage de vérification SystemVerilog UVM.\nExpérience avec différents langages de script tel que Python, Perl, Ruby, etc.\nConnaissance de base des protocoles de transfert de données tel que PCIe, USB, SATA, Ethernet, Display Port, HDMI.\nConnaissance de base des techniques de vérification formelle.\nConnaissance de base des composantes mixtes (analogiques/numériques).\nCadence est une employeuse qui souscrit à l’égalité des chances et qui s’engage à embaucher une main-d’oeuvre diversifiée.\nThe annual salary range for MOUNT-ROYAL 01 (Montreal)is 89,600.00 - 166,400.00 CAD Annual CAD Annual. You may also be eligible to receive incentive compensation: bonus, equity, and benefits. Please note that the salary range is a guideline and compensation may vary based on factors such as qualifications, skill level, competencies and work location.\nOur benefits programs include: paid vacation and holidays, leave of absence programs, Registered Retirement Savings Plan (RRSP), Tax Free Savings (TFSA) plan for post-tax investment savings, Employee Stock Purchase Plan, group health coverage that includes dental, vision and Emotional Wellbeing Support (EAP) benefits for you and your eligible dependents. Cadence also offers employee and dependent Life insurance, and short-term and long-term disability. In addition, Cadence provides Global Travel Medical coverage, Business Travel Accident Insurance, and a funded Lifestyle Spending Account (LSA).\nWe’re doing work that matters. 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