{"id":326357,"url":"https://alion.io/job/cadence-design-systems-lead-solutions-engineer-2","title":"Lead Solutions Engineer","company":{"id":4351,"name":"Cadence Design Systems","domain":"cadence.com","url":"https://alion.io/company/cadence","size_band":"5000+","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Workday","truth_index":{"grade":"B","score":81,"open_postings":108,"ghost_share":0,"stale_share":0.759,"repost_share":0,"time_to_fill_p50_days":59,"computed_at":"2026-11-05T05:54:30Z"}},"role":"Solutions","role_family":"Solutions","seniority":"lead","employment_type":"full_time","work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Bengaluru, India"],"countries":["IN"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":{"min_usd":28000,"max_usd":67000,"period":"year","method":"role_seniority_country_remote_cell","sample_n":8},"experience_years_min":null,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"C++","optional":false},{"name":"Perl","optional":false},{"name":"Python","optional":false},{"name":"SystemVerilog","optional":false},{"name":"UVM","optional":false},{"name":"Verilog","optional":false},{"name":"VHDL","optional":false},{"name":"Assembly","optional":true},{"name":"C","optional":true},{"name":"Embedded C","optional":true},{"name":"Formal Verification","optional":true}],"status":"live","first_seen_at":"2024-05-01T00:00:00Z","employer_posted_date":"2024-05-01","last_verified_at":"2026-11-05T22:57:11Z","board_verified":true,"closed_at":null,"days_open":919,"trust":{"level":"stale","repost_count":0,"flags":["stale"],"days_open":918},"description":"At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.\nUnderstand/review Design specification and develop verification strategy/Test plan/coverage plan. Development of constrained random verification environments and verification components. Writing tests/sequences/functional coverage/assertions to meet verification goals. Developing c-based test cases for SOC verification.\nRequired experience\nStrong background on functional verification fundamentals, environment planning, test plan generation, environment development\nSystem Verilog experience and experience with UVM based functional verification environment development is required.\nGood knowledge of verilog/vhdl/C/C++/Perl/Python.\nExpertise in AMBA protocols. (AXI/AHB/APB).\nGood knowledge of at least one of the USB/PCIE/Ethernet/DDR/LPDDR or similar protocols\nGood handle on using one or more version control software\nGood handle on using one or more load sharing software\nDesirable skills and experience\nPrior experience with Cadence tools and flows is highly desirable.\nFamiliarity with ARM/CPU architectures is a plus.\nExperience in developing c-based test cases for SOC verification\nSome experience with assembly language programming\nGood knowledge of some of the protocols like UART, I2C, SPI, JTAG\nEmbedded C code development and debug\nFormal Verification experience\nStrong vocabulary, communication, organizational, planning, and presentation skills are essential. Ability to work independently and productively with high quality output and results in a fast paced and dynamic environment. Ability and desire to learn new methodologies, languages, protocols etc. Must be open to constant personal development and growth to meet the evolving demands of the semiconductor industry. Self-motivated and willing take up additional responsibilities to contribute to team’s success.\nWe’re doing work that matters. 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