{"id":1145703,"url":"https://alion.io/job/cadence-design-systems-lead-verification-engineer-2","title":"Lead Verification Engineer","company":{"id":4351,"name":"Cadence Design Systems","domain":"cadence.com","url":"https://alion.io/company/cadence","size_band":"5000+","is_staffing_agency":false,"is_intermediary":false,"ats_vendor":"Workday","truth_index":{"grade":"B","score":83,"open_postings":71,"ghost_share":0,"stale_share":0.662,"repost_share":0,"time_to_fill_p50_days":49,"computed_at":"2026-09-23T05:45:00Z"}},"role":"Hardware","role_family":"Hardware","seniority":"lead","employment_type":"full_time","work_mode":"on_site","remote_scope":null,"hiring_geo_confidence":"structured","locations":["Noida, India"],"countries":["IN"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":{"min_usd":42000,"max_usd":100000,"period":"year","method":"global_role_cell_scaled_by_country","sample_n":344},"experience_years_min":3,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"C++","optional":false},{"name":"Cadence Palladium","optional":false},{"name":"SystemVerilog","optional":false},{"name":"UVM","optional":false},{"name":"Verilog","optional":false},{"name":"VHDL","optional":false}],"status":"live","first_seen_at":"2026-09-23T14:59:28Z","employer_posted_date":"2026-09-23","last_verified_at":"2026-09-23T23:42:18Z","board_verified":true,"closed_at":null,"days_open":0,"trust":{"level":"ok","repost_count":null,"flags":[],"days_open":0},"description":"At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.\nCadence is a pivotal leader in electronic design, building upon more than 30 years of computational software expertise. The company applies its underlying Intelligent System Design strategy to deliver software, hardware and IP that turn design concepts into reality. Cadence customers are the world’s most innovative companies, delivering extraordinary electronic products from chips to boards to systems for the most dynamic market applications including consumer, hyperscale computing, 5G communications, automotive, aerospace industrial and health.\nThe Cadence Advantage\nThe opportunity to work on cutting-edge technology in an environment that encourages you to be creative, innovative, and to make an impact.\nCadence’s employee-friendly policies focus on the physical and mental well-being of employees, career development, providing opportunities for learning, and celebrating success in recognition of specific needs of the employees.\nThe unique “One Cadence - One Team” culture promotes collaboration within and across teams to ensure customer success\nMultiple avenues of learning and development available for employees to explore as per their specific requirement and interests\nYou get to work with a diverse team of passionate, dedicated, and talented individuals who go above and beyond for our customers, our communities, and each other-every day.\nJob Summary:\nWe are looking for a candidate with excellent communication skills and ability to ramp up on new technologies quickly and independently. This position requires the technical expertise in Emulation domain. This an excellent opportunity to work in a supportive and friendly work environment, where we are vested in each other’s success, and are passionate about technology and innovation.\nPosition Description:\nProduct validation engineer to work on key Palladium technologies including UPF. Position is based in Noida/Bangalore.\nRole involves verification of various upcoming features in Palladium.\nWork also involves managing current set of regressions.\nParticipate in technical discussions, including Functional Specification reviews, Testplan reviews etc\nReview and guide team members on technical deliverables from the team\nPerson will be fully responsible and accountable for quality of releases and features for Palladium emulation technology.\nMentor juniors in the team\nContribute towards the improvement of existing emulation validation/verification flows \nPosition Requirements:\nThe person should be an Electrical, Electronics or Computer Science Engineer with very good understanding of HDLs (Verilog and/ or VHDL).\nPrior experience in Emulation/UPF will be big plus. He/ she should have a good working knowledge of EDA tools (Cadence/ Others) specially Palladium with focus towards debugging design/ verification problems.\nExperience in process automation with scripting.\nExperience with SystemVerilog, C++, UVM.\nExperience with Functional Verification of complex digital systems, e.g. SoC Verification, with a Hardware Verification Language (HVL) like SystemVerilog.\nB. Tech/BE/ M. Tech / ME with 3+ years of relevant experience\nBehavioral skills required:\nMust possess strong written, verbal and presentation skills.\nGood communication and interpersonal skills, demonstrate teamwork and collaboration skills.\nAbility to establish a close working relationship with both customer peers and management.\nExplore what’s possible to get the job done, including creative use of unconventional solutions\nWork effectively across functions and geographies\nPush to raise the bar while always operating with integrity\nWe’re doing work that matters. Help us solve what others can’t.","description_format":"text","description_chars":3765,"description_truncated":false,"requirements":{"experience_years_min":3,"management_years_min":null,"team_size_min":null,"manages_managers":false,"education":null,"security_clearance":false,"languages":[]},"benefits":[],"hiring_locations":[],"hiring_excludes":[],"relocation_offered":false,"industries":["Wireless"],"lifecycle":[{"event":"open","at":"2026-09-23T14:59:28Z"}],"liveness":{"score":86,"band":"hot","label":"Hiring now","p_open":1,"p_active":0.86,"p_room":1,"age_days":0,"expected_fill_days":49,"reasons":["conf:0","win:early","comp:brand"],"computed_at":"2026-09-24T00:05:31Z"},"pay":null,"html_url":"https://alion.io/job/cadence-design-systems-lead-verification-engineer-2","json_url":"https://alion.io/job/cadence-design-systems-lead-verification-engineer-2.json","meta":{"generated_at":"2026-09-24T00:05:31Z","cache_seconds":300,"methodology":"https://alion.io/methodology","terms":"https://alion.io/terms","contact":"https://alion.io/contact","api":"https://alion.io/developers"}}