{"id":2870684,"url":"https://alion.io/job/cadence-design-systems-principal-design-engineer-11","title":"Principal Design Engineer","company":{"id":4351,"name":"Cadence Design Systems","domain":"cadence.com","url":"https://alion.io/company/cadence","size_band":"5000+","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Workday","truth_index":{"grade":"B","score":82,"open_postings":111,"ghost_share":0,"stale_share":0.73,"repost_share":0,"time_to_fill_p50_days":56,"computed_at":"2026-10-21T05:46:15Z"}},"role":"Hardware","role_family":"Hardware","seniority":"lead","employment_type":"full_time","work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Austin, United States"],"countries":["US"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":{"min_usd":171000,"max_usd":325000,"period":"year","method":"role_seniority_country_remote_cell","sample_n":609},"experience_years_min":8,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"SystemVerilog","optional":false},{"name":"Verilog","optional":false},{"name":"Cadence Xcelium","optional":true},{"name":"Perl","optional":true},{"name":"Python","optional":true}],"status":"live","first_seen_at":"2026-09-09T00:00:00Z","employer_posted_date":"2026-09-09","last_verified_at":"2026-10-21T17:01:53Z","board_verified":true,"closed_at":null,"days_open":42,"trust":{"level":"ok","repost_count":null,"flags":[],"days_open":42},"description":"At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.\n#### Responsibilities:\n* Design and integration of IPs in SoC based on high-level architectural specifications from customers.\n* Perform Lint/CDC checks on the design for quality assurance and resolve related issues.\n* Create synthesis constraints for the design at the IP and SoC level and perform basic synthesis for PPA (Power, Performance, Area) optimization.\n* Create detailed Microarchitectural Specification documents for the design.\n* Provide support to the verification team for test plan creation, coverage analysis, and feature debugging.\n* Provide support to the physical design team as needed for design implementation.\n* Implement innovative solutions to automate repetitive tasks.\n* Collaborate within and across teams for effective project execution.\n#### Requirements:\n* B.E./B.Tech/M.Tech with at least 8-12 years of experience as a digital design engineer.\n* Strong knowledge of digital design fundamentals and Verilog/SystemVerilog (SV).\n* Solid knowledge of Lint/CDC tools and the ability to set up flows from scratch.\n* Knowledge of creating synthesis constraints and Static Timing Analysis (STA); familiarity with synthesis tools is a plus.\n* Familiarity with simulation tools (e.g., Xcelium, Verisium) to support verification.\n* Experience with AMBA protocols and other ARM IPs is a plus.\n* Experience with high-speed IPs such as PCIe, Ethernet, and DDR is a plus.\n* Proficiency in scripting languages (Python/Perl/Tcl).\n* Ability to innovate and automate repetitive tasks.\n* Good communication skills for effective cross-functional collaboration.\nWe’re doing work that matters. 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