{"id":2870699,"url":"https://alion.io/job/cadence-design-systems-principal-design-engineer-13","title":"Principal Design Engineer","company":{"id":4351,"name":"Cadence Design Systems","domain":"cadence.com","url":"https://alion.io/company/cadence","size_band":"5000+","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Workday","truth_index":{"grade":"B","score":82,"open_postings":114,"ghost_share":0,"stale_share":0.728,"repost_share":0,"time_to_fill_p50_days":57,"computed_at":"2026-10-27T05:46:45Z"}},"role":"Industrial Engineering","role_family":"Industrial Engineering","seniority":"lead","employment_type":"full_time","work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Hyderabad, India"],"countries":["IN"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":{"min_usd":20000,"max_usd":51000,"period":"year","method":"role_seniority_country_remote_cell","sample_n":14},"experience_years_min":8,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[],"status":"live","first_seen_at":"2026-08-06T00:00:00Z","employer_posted_date":"2026-08-06","last_verified_at":"2026-10-28T00:32:27Z","board_verified":true,"closed_at":null,"days_open":83,"trust":{"level":"ok","repost_count":null,"flags":[],"days_open":83},"description":"At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.\nRole Summary\nWe are looking for an experienced Principal Analog Design Engineer to drive the design and delivery of high-speed interface IPs, with a strong emphasis on Die-to-Die (D2D) interconnects based on the UCIe standard and advanced package technologies. The role requires hands-on ownership from architecture through silicon bring-up, working closely with layout, verification, package, and system teams.\nKey Responsibilities\nArchitect, design, and deliver high-speed analog / mixed-signal circuits for Die-to-Die and chiplet-based systems, including UCIe-compliant interfaces.\nOwn analog blocks for high-speed interfaces such as clocking, TX/RX front-ends, termination schemes, biasing, and equalization support circuits.\nDrive architecture definition, feasibility analysis, and design trade-offs considering signal integrity, power, noise, and packaging parasitics.\nPerform schematic design, simulation, and optimization across PVT corners using industry-standard EDA tools.\nWork closely with advanced package teams (2.5D / 3D, interposers, organic substrates) to co-optimize circuit and package design.\nSupport layout reviews, parasitic extraction analysis, and post-layout sign-off for high-speed performance.\nCollaborate with AMS verification, digital, and system teams to enable full-chip integration and validation.\nParticipate in silicon bring-up, debug, and characterization, including correlation with simulation results.\nContribute to design methodology, checklists, and best practices for high-speed analog and D2D designs.\nRequired Qualifications\nBachelor’s or Master’s degree in Electrical / Electronics Engineering or related field.\n8+ years of hands-on experience in analog / mixed-signal IC design.\nStrong experience with high-speed interface design (e.g., DDR, PCIe, SerDes, Die-to-Die links).\nSolid understanding of UCIe standard concepts, D2D PHY requirements, and chiplet architectures.\nExperience working with advanced packaging technologies and understanding package-induced effects on high-speed signaling.\nProficiency in schematic-level design, simulation, and debug across PVT corners.\nStrong fundamentals in analog circuit theory, signal integrity, noise analysis, and clocking.\nPreferred / Nice-to-Have Skills\nDirect hands-on experience with UCIe PHY design or integration.\nExposure to AMS verification flows and mixed-signal simulation environments.\nExperience with post-silicon debug and correlation.\nKnowledge of power integrity, thermal considerations, and package-aware design flows.\nAbility to mentor junior engineers and lead technical discussions.\nWhat Success Looks Like\nRobust, scalable UCIe / D2D analog IPs meeting performance, power, and reliability targets.\nSmooth collaboration across design, verification, and packaging teams.\nPredictable execution aligned with project milestones and KPIs / OKRs.\nStrong ownership mindset from architecture to silicon.\nWe’re doing work that matters. Help us solve what others can’t.","description_format":"text","description_chars":3077,"description_truncated":false,"requirements":{"experience_years_min":8,"management_years_min":null,"team_size_min":null,"manages_managers":false,"education":{"level":"bachelor","optional":false},"security_clearance":false,"languages":[]},"benefits":[],"hiring_locations":[],"hiring_excludes":[],"relocation_offered":false,"industries":["EDA Software","Semiconductor IP & Chip Design Services"],"lifecycle":[{"event":"open","at":"2026-10-19T19:31:48Z"}],"visa":[],"liveness":{"score":15,"band":"cold","label":"Long shot","p_open":1,"p_active":0.345,"p_room":0.44,"age_days":82,"expected_fill_days":57,"reasons":["conf:2","stale_co","evergreen","wave","velocity","win:tail","crowd:brand"],"computed_at":"2026-10-27T05:46:45Z"},"pay":null,"html_url":"https://alion.io/job/cadence-design-systems-principal-design-engineer-13","json_url":"https://alion.io/job/cadence-design-systems-principal-design-engineer-13.json","meta":{"generated_at":"2026-10-28T01:43:03Z","cache_seconds":300,"methodology":"https://alion.io/methodology","terms":"https://alion.io/terms","contact":"https://alion.io/contact","api":"https://alion.io/developers","about":"Alion is a live layer of people, companies and AI agents: who they are, whether they are real and active right now, what they do and how to work with them, readable by people and by agents and paid per call.","catalog":"https://alion.io/catalog.json","usage":{"tier":"crawler_verified","counted_by":"address","units_charged":1,"used_today":2259,"day_limit":null,"remaining_today":null,"minute_limit":300,"resets_at":"2026-10-29T00:00:00Z"}},"offers":[{"id":"company.slices","title":"One company in depth, by slice","status":"live","price":{"credits":0.02,"usd":0.002,"plus_per_slice":{"credits":0.05,"usd":0.005}},"unit":"per company, plus each slice with data","note":"the employer in depth","call":{"mcp_tool":"get_company","arguments":{"id":4351},"rest":"https://alion.io/mcp/rest/get_company?id=4351"},"human":"https://alion.io/catalog?offer=company.slices&for=job%2Fcadence-design-systems-principal-design-engineer-13"},{"id":"market.stats","title":"A market slice: pay, demand and time to fill","status":"live","price":{"credits":1,"usd":0.1},"unit":"per slice","note":"pay, demand and time to fill for this role and place","call":{"mcp_tool":"market_stats"},"human":"https://alion.io/catalog?offer=market.stats&for=job%2Fcadence-design-systems-principal-design-engineer-13"},{"id":"job.search","title":"Open jobs by role, technology, place, pay and visa","status":"live","price":{"credits":0.02,"usd":0.002},"unit":"per posting in a list","note":"similar open postings","call":{"mcp_tool":"search_jobs"},"human":"https://alion.io/catalog?offer=job.search&for=job%2Fcadence-design-systems-principal-design-engineer-13"},{"id":"company.verify","title":"Is this company real and active right now","status":"pilot","price":null,"unit":"per company","request":{"url":"https://alion.io/catalog/request","method":"POST","body":"{\"offer\": \"company.verify\", \"for\": \"job/cadence-design-systems-principal-design-engineer-13\", \"note\": \"what you need it for\"}"},"human":"https://alion.io/catalog?offer=company.verify&for=job%2Fcadence-design-systems-principal-design-engineer-13"}]}