{"id":2870723,"url":"https://alion.io/job/cadence-design-systems-principal-design-engineer-15","title":"Principal Design Engineer","company":{"id":4351,"name":"Cadence Design Systems","domain":"cadence.com","url":"https://alion.io/company/cadence","size_band":"5000+","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Workday","truth_index":{"grade":"B","score":82,"open_postings":112,"ghost_share":0,"stale_share":0.723,"repost_share":0,"time_to_fill_p50_days":57,"computed_at":"2026-10-28T05:59:10Z"}},"role":"Hardware","role_family":"Hardware","seniority":"lead","employment_type":"full_time","work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Bengaluru, India"],"countries":["IN"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":{"min_usd":31000,"max_usd":70000,"period":"year","method":"global_role_cell_scaled_by_country","sample_n":796},"experience_years_min":7,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"C++","optional":false},{"name":"Python","optional":false},{"name":"SystemVerilog","optional":false},{"name":"Git","optional":true}],"status":"live","first_seen_at":"2026-02-06T00:00:00Z","employer_posted_date":"2026-02-06","last_verified_at":"2026-10-28T18:57:44Z","board_verified":true,"closed_at":null,"days_open":265,"trust":{"level":"stale","repost_count":0,"flags":["stale"],"days_open":264},"description":"At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.\nJob Description\nThis is an opportunity to join a dynamic and growing team of experienced engineers developing high-performance physical IP for industry-standard protocols. The successful candidate will be a highly motivated self-starter who is able to work independently and collaboratively to complete tasks within required project timelines with high quality. The candidate will contribute to digital architecture, digital RTL, low power design, synthesis and timing analysis, and behavioral coding for all IPs in the SerDes physical IP portfolio as well as executing various tool flows for IP quality control. The candidate will be able to work as part of a small and focused team of engineers and will be able to collaborate successfully as needed with design architects, digital verification, project management, and digital and analog design teams in multiple worldwide geographies.\nThis includes but is not limited to:\nDigital architecture that has an understanding of the trade-offs for power, performance, and area\n\nDrive architecture to micro-architecture to RTL implementation with the refining of features/requirements throughout the design process\n\nUnderstanding of synthesis, constraint generation, power management and DFT\n\nUnderstanding of low-power designs and features (power islands, state retention, isolation)\n\nWork with verification team to specify coverage points, testing strategy, corner conditions and stimulus creation\n\nFamiliarity with uC Based subsystems and their architecture\n\nQualifications\n7+ Years’ experience in working with Digital Design and Architecture.\n\nMust have good written and verbal cross-functional communication skills.\n\nProven experience in most of the following:\nDesign Architecture\n\nDesign implementation\n\nEmbedded uC Designs\n\nSynthesis and SDC Creation\n\nScripting of design automation\n\nDebugging verification test cases / SVA’s to cover the design\n\nKnowledge of existing Serial standards such as PCIE, USB, Ethernet, etc.\n\nMust be comfortable interacting across the IPG development team including the ability to work with Mixed-signal, Verification and Analog teams\n\nKnowledge of multiple programming languages. System Verilog, Python, C/C++, etc, are a plus\n\nWorking knowledge of revision control tools such as Perforce, Git, SVN is a plus\n\nEducation Level: Bachelor's Degree (MSEE Preferred)\n\nWe’re doing work that matters. Help us solve what others can’t.","description_format":"text","description_chars":2519,"description_truncated":false,"requirements":{"experience_years_min":7,"management_years_min":null,"team_size_min":null,"manages_managers":false,"education":{"level":"bachelor","optional":false},"security_clearance":false,"languages":[]},"benefits":[],"hiring_locations":[],"hiring_excludes":[],"relocation_offered":false,"industries":["EDA Software","Semiconductor IP & Chip Design Services"],"lifecycle":[{"event":"open","at":"2026-10-19T19:31:48Z"}],"visa":[],"liveness":{"score":6,"band":"cold","label":"Long shot","p_open":1,"p_active":0.227,"p_room":0.28,"age_days":264,"expected_fill_days":57,"reasons":["conf:5","stale_co","evergreen","wave","velocity","win:tail","crowd:brand"],"computed_at":"2026-10-28T05:59:10Z"},"pay":null,"html_url":"https://alion.io/job/cadence-design-systems-principal-design-engineer-15","json_url":"https://alion.io/job/cadence-design-systems-principal-design-engineer-15.json","meta":{"generated_at":"2026-10-29T04:45:41Z","cache_seconds":300,"methodology":"https://alion.io/methodology","terms":"https://alion.io/terms","contact":"https://alion.io/contact","api":"https://alion.io/developers","about":"Alion is a live layer of people, companies and AI agents: who they are, whether they are real and active right now, what they do and how to work with them, readable by people and by agents and paid per call.","catalog":"https://alion.io/catalog.json","usage":{"tier":"crawler_verified","counted_by":"address","units_charged":1,"used_today":7393,"day_limit":null,"remaining_today":null,"minute_limit":300,"resets_at":"2026-10-30T00:00:00Z"}},"offers":[{"id":"company.slices","title":"One company in depth, by slice","status":"live","price":{"credits":0.02,"usd":0.002,"plus_per_slice":{"credits":0.05,"usd":0.005}},"unit":"per company, plus each slice with data","note":"the employer in depth","call":{"mcp_tool":"get_company","arguments":{"id":4351},"rest":"https://alion.io/mcp/rest/get_company?id=4351"},"human":"https://alion.io/catalog?offer=company.slices&for=job%2Fcadence-design-systems-principal-design-engineer-15"},{"id":"market.stats","title":"A market slice: pay, demand and time to fill","status":"live","price":{"credits":1,"usd":0.1},"unit":"per slice","note":"pay, demand and time to fill for this role and place","call":{"mcp_tool":"market_stats"},"human":"https://alion.io/catalog?offer=market.stats&for=job%2Fcadence-design-systems-principal-design-engineer-15"},{"id":"job.search","title":"Open jobs by role, technology, place, pay and visa","status":"live","price":{"credits":0.02,"usd":0.002},"unit":"per posting in a list","note":"similar open postings","call":{"mcp_tool":"search_jobs"},"human":"https://alion.io/catalog?offer=job.search&for=job%2Fcadence-design-systems-principal-design-engineer-15"},{"id":"company.verify","title":"Is this company real and active right now","status":"pilot","price":null,"unit":"per company","request":{"url":"https://alion.io/catalog/request","method":"POST","body":"{\"offer\": \"company.verify\", \"for\": \"job/cadence-design-systems-principal-design-engineer-15\", \"note\": \"what you need it for\"}"},"human":"https://alion.io/catalog?offer=company.verify&for=job%2Fcadence-design-systems-principal-design-engineer-15"}],"agent":{"mcp":"https://alion.io/mcp/jobs","mcp_open":"https://alion.io/mcp/open","next":[{"tool":"get_job","arguments":{"id":2870723}},{"tool":"search_jobs","arguments":{"company":"cadence.com","detail":"compact"}},{"tool":"match_people","arguments":{"job_id":2870723},"note":"people open to offers who fit this vacancy"}],"note":"The same data through MCP tools: https://alion.io/mcp/open needs no sign-in (compact searches, postings, people); https://alion.io/mcp with an Alion account has everything. Docs: https://alion.io/developers"}}