{"id":326352,"url":"https://alion.io/job/cadence-design-systems-principal-design-engineer-6","title":"Principal Design Engineer","company":{"id":4351,"name":"Cadence Design Systems","domain":"cadence.com","url":"https://alion.io/company/cadence","size_band":"5000+","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Workday","truth_index":{"grade":"B","score":81,"open_postings":109,"ghost_share":0,"stale_share":0.78,"repost_share":0,"time_to_fill_p50_days":58,"computed_at":"2026-11-12T10:38:37Z"}},"role":"Hardware","role_family":"Hardware","seniority":"lead","employment_type":"full_time","work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Brussels, Belgium"],"countries":["BE"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":{"min_usd":113000,"max_usd":257000,"period":"year","method":"global_role_cell_scaled_by_country","sample_n":796},"experience_years_min":8,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"C++","optional":false},{"name":"Matplotlib","optional":false},{"name":"Pandas","optional":false},{"name":"Python","optional":false},{"name":"SystemC","optional":false},{"name":"UVM","optional":false},{"name":"Verilog","optional":false}],"status":"live","first_seen_at":"2024-11-06T00:00:00Z","employer_posted_date":"2024-11-06","last_verified_at":"2026-11-12T13:51:21Z","board_verified":true,"closed_at":null,"days_open":736,"trust":{"level":"stale","repost_count":0,"flags":["stale"],"days_open":736},"description":"At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.\nPerformance Modeling Engineer\nLocation - India (Pune)\nSummary\nWe are looking for modeling engineers to help develop performance models, perform architectural tradeoff analysis, and enable data driven design decisions for our next generation DDR memory controller architectures that can meet today’s complex SoC and workload requirements. Hardware modelling experience (C++/SystemC/TLM/Python) and computer architecture foundation is desired.\nResponsibilities\nDevelop cycle-level performance models in SystemC or C++\nCorrelate performance models to match RTL configurations and traffic conditions\nWork with Memory Architects to understand feature requirements, architectural specifications and implement in the model\nAnalyze architectural trade-offs (throughput, hardware cost) across different scenarios and architectural choices\nDevelop synthetic memory traffic/traces that are representative of real-world applications (CPU, GPU, DSP, NoC, etc)\nDevelop scripts to automate generation of various performance metrics and statistics post RTL simulation that helps identify performance bottlenecks\nRequired Skills\nBE/B.Tech ME/M.Tech in ECE, E&TC, CS or similar\n8+ years of experience in hardware modeling, functional or performance\nStrong coding skills in C++, SystemC and Transaction Level Modeling (TLM)\nBasic understanding of performance principles, Queuing Theory, throughput/latency tradeoffs\nAdditional Skills\nUnderstand RTL-Verilog, SV, UVM and experience analyzing waveforms\nUnderstand memory protocols and timing - DDR4, DDR5, LP4, LP5\nExperience using performance simulators - Memory Controller, NoC, CPU models\nCoding in Python and familiarity with packages like Pandas, Matplotlib\nExperience working with performance benchmarks - SPEC, STREAM, etc\nConcepts related to Quality of Service (QoS) and how memory controller can tradeoff performance and latencies\nWe’re doing work that matters. Help us solve what others can’t.","description_format":"text","description_chars":2042,"description_truncated":false,"requirements":{"experience_years_min":8,"management_years_min":null,"team_size_min":null,"manages_managers":false,"education":null,"security_clearance":false,"languages":[]},"benefits":[],"hiring_locations":[{"name":"India","iso":"IN","kind":"country"}],"hiring_excludes":[],"relocation_offered":false,"industries":["EDA Software","Semiconductor IP & Chip Design Services"],"lifecycle":[{"event":"open","at":"2026-09-05T16:54:50Z"}],"visa":[],"liveness":{"score":4,"band":"cold","label":"Long shot","p_open":1,"p_active":0.136,"p_room":0.28,"age_days":736,"expected_fill_days":58,"reasons":["conf:3","stale_co","evergreen","velocity","win:tail","crowd:brand"],"computed_at":"2026-11-12T10:38:37Z"},"pay":null,"html_url":"https://alion.io/job/cadence-design-systems-principal-design-engineer-6","json_url":"https://alion.io/job/cadence-design-systems-principal-design-engineer-6.json","meta":{"generated_at":"2026-11-12T16:41:02Z","cache_seconds":300,"methodology":"https://alion.io/methodology","terms":"https://alion.io/terms","contact":"https://alion.io/contact","api":"https://alion.io/developers","about":"Alion is a live layer of people, companies and AI agents: who they are, whether they are real and active right now, what they do and how to work with them, readable by people and by agents and paid per call.","catalog":"https://alion.io/catalog.json","usage":{"tier":"crawler_verified","counted_by":"address","units_charged":1,"used_today":35007,"day_limit":null,"remaining_today":null,"minute_limit":300,"resets_at":"2026-11-13T00:00:00Z"}},"offers":[{"id":"company.slices","title":"One company in depth, by slice","status":"live","price":{"credits":0.1,"usd":0.01,"plus_per_slice":{"credits":0.05,"usd":0.005}},"unit":"per company, plus each slice with data","note":"the employer in depth","call":{"mcp_tool":"get_company","arguments":{"id":4351},"rest":"https://alion.io/mcp/rest/get_company?id=4351"},"human":"https://alion.io/catalog?offer=company.slices&for=job%2Fcadence-design-systems-principal-design-engineer-6"},{"id":"market.stats","title":"A market slice: pay, demand and time to fill","status":"live","price":{"credits":2,"usd":0.2},"unit":"per slice","note":"pay, demand and time to fill for this role and place","call":{"mcp_tool":"market_stats"},"human":"https://alion.io/catalog?offer=market.stats&for=job%2Fcadence-design-systems-principal-design-engineer-6"},{"id":"job.search","title":"Open jobs by role, technology, place, pay and visa","status":"live","price":{"credits":0.1,"usd":0.01},"unit":"per posting in a list","note":"similar open postings","call":{"mcp_tool":"search_jobs"},"human":"https://alion.io/catalog?offer=job.search&for=job%2Fcadence-design-systems-principal-design-engineer-6"},{"id":"company.verify","title":"Is this company real and active right now","status":"pilot","price":null,"unit":"per company","request":{"url":"https://alion.io/catalog/request","method":"POST","body":"{\"offer\": \"company.verify\", \"for\": \"job/cadence-design-systems-principal-design-engineer-6\", \"note\": \"what you need it for\"}"},"human":"https://alion.io/catalog?offer=company.verify&for=job%2Fcadence-design-systems-principal-design-engineer-6"}],"agent":{"mcp":"https://alion.io/mcp/jobs","mcp_open":"https://alion.io/mcp/open","next":[{"tool":"get_job","arguments":{"id":326352}},{"tool":"search_jobs","arguments":{"company":"cadence.com","detail":"compact"}},{"tool":"match_people","arguments":{"job_id":326352},"note":"people open to offers who fit this vacancy"}],"note":"The same data through MCP tools: https://alion.io/mcp/open needs no sign-in (compact searches, postings, people); https://alion.io/mcp with an Alion account has everything. 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