{"id":1640049,"url":"https://alion.io/job/cadence-design-systems-principal-design-engineer-9","title":"Principal Design Engineer","company":{"id":4351,"name":"Cadence Design Systems","domain":"cadence.com","url":"https://alion.io/company/cadence","size_band":"5000+","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Workday","truth_index":{"grade":"B","score":82,"open_postings":110,"ghost_share":0,"stale_share":0.727,"repost_share":0,"time_to_fill_p50_days":57,"computed_at":"2026-10-22T06:10:10Z"}},"role":"Hardware","role_family":"Hardware","seniority":"lead","employment_type":"full_time","work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Austin, United States"],"countries":["US"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":{"min_usd":172000,"max_usd":326000,"period":"year","method":"role_seniority_country_remote_cell","sample_n":609},"experience_years_min":8,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"Cadence Xcelium","optional":false},{"name":"Formal Verification","optional":false},{"name":"SystemVerilog","optional":false},{"name":"UVM","optional":false}],"status":"live","first_seen_at":"2026-10-01T21:55:35Z","employer_posted_date":"2026-10-01","last_verified_at":"2026-10-22T06:53:03Z","board_verified":true,"closed_at":null,"days_open":20,"trust":{"level":"ok","repost_count":null,"flags":[],"days_open":20},"description":"At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.\nRequired Qualifications\nB.E./B.Tech or M.Tech/M.S. in Electronics, VLSI, or related field\n8-10 years of hands-on DV experience in semiconductor/ASIC/SoC companies\nDeep expertise in SystemVerilog and UVM (Universal Verification Methodology)\nStrong understanding of digital design fundamentals - RTL, timing, clocking, resets\nExperience with industry-standard simulators: Xcelium, VCS, Questa\nProficiency in coverage-driven verification - functional, code, and toggle coverage\nHands-on experience with formal verification tools and flows\nExperience with bus protocols such as AXI, AHB, APB, PCIe, DDR, or similar\nStrong debug skills - waveform analysis (Verisium, SimVision)\nFamiliarity with low-power verification (UPF/CPF) and gls/power-aware gls simulation\nCore Responsibilities\nStrategy and Architecture\nVerification Planning: Define the overall verification strategy, including the choice of methodology (typically UVM/SystemVerilog), tools, and infrastructure.\nTestbench Architecture: Design scalable, reusable, and robust verification environments. This includes developing Bus Functional Models (BFMs), monitors, scoreboards, and checkers.\nFeature Extraction: Analyze architectural specifications to identify critical features and corner cases that require rigorous testing.\nExecution and Technical Leadership\nCustomer Interaction: Technically lead DV execution of small to mid-sized customer ASIC projects. Handle customer interactions. Convert high level customer requirements into DV execution plan.\nDevelopment: Write complex test cases and sequences to achieve high functional coverage.\nDebug: Lead the root-cause analysis of complex design bugs, collaborating closely with design engineers to implement fixes.\nConstraint Random Testing: Implement constrained-random stimulus generation to explore the design space beyond directed tests.\nFormal Verification: Utilize formal tools to prove specific properties or find deep-seated bugs that simulation might miss.\nMetric Management\nCoverage Analysis: Monitor and analyze functional and code coverage metrics.\nGate-Level Simulation (GLS): Oversee simulations on the synthesized netlist to verify timing and reset behavior.\nSign-off: Define the \"definition of done\" and provide final technical approval for the verification phase.\nSoft Skills and Leadership\nMentorship: Guiding junior engineers on coding standards and debugging techniques.\nCross-functional Collaboration: Acting as the primary technical point of contact between the design, architecture, and emulation teams.\nProject Management: Managing timelines, identifying risks in the verification schedule, and prioritizing tasks to meet project deadlines.\nWe’re doing work that matters. Help us solve what others can’t.","description_format":"text","description_chars":2845,"description_truncated":false,"requirements":{"experience_years_min":8,"management_years_min":null,"team_size_min":null,"manages_managers":false,"education":{"level":"master","optional":false},"security_clearance":false,"languages":[]},"benefits":[],"hiring_locations":[],"hiring_excludes":[],"relocation_offered":false,"industries":["EDA Software","Semiconductor IP & Chip Design Services"],"lifecycle":[{"event":"open","at":"2026-10-01T21:55:35Z"}],"visa":[{"country":"US","licensed_sponsor":true,"evidence":"H-1B filings in 12 months: 368 · green card filings: 176","filings_12m":368,"filings_prev_12m":268,"green_card_filings_12m":176,"median_offered_wage_usd":150882,"route":null,"cap_exempt":false,"checked_at":"2026-10-15T11:24:14+00:00","sources":["US Department of Labor: LCA disclosure data (H-1B, H-1B1, E-3)","US Department of Labor: PERM disclosure data (green cards)"],"filings_for_role_12m":117}],"liveness":{"score":35,"band":"fade","label":"Fading","p_open":1,"p_active":0.393,"p_room":0.9,"age_days":20,"expected_fill_days":57,"reasons":["conf:3","stale_co","evergreen","wave","velocity","win:mid","comp:brand"],"computed_at":"2026-10-22T06:10:10Z"},"pay":null,"html_url":"https://alion.io/job/cadence-design-systems-principal-design-engineer-9","json_url":"https://alion.io/job/cadence-design-systems-principal-design-engineer-9.json","meta":{"generated_at":"2026-10-22T12:12:17Z","cache_seconds":300,"methodology":"https://alion.io/methodology","terms":"https://alion.io/terms","contact":"https://alion.io/contact","api":"https://alion.io/developers","about":"Alion is a live layer of people, companies and AI agents: who they are, whether they are real and active right now, what they do and how to work with them, readable by people and by agents and paid per call.","catalog":"https://alion.io/catalog.json","usage":{"tier":"crawler_verified","counted_by":"address","units_charged":1,"used_today":10535,"day_limit":null,"remaining_today":null,"minute_limit":300,"resets_at":"2026-10-23T00:00:00Z"}},"offers":[{"id":"company.slices","title":"One company in depth, by slice","status":"live","price":{"credits":0.02,"usd":0.002,"plus_per_slice":{"credits":0.05,"usd":0.005}},"unit":"per company, plus each slice with data","note":"the employer in depth","call":{"mcp_tool":"get_company","arguments":{"id":4351},"rest":"https://alion.io/mcp/rest/get_company?id=4351"},"human":"https://alion.io/catalog?offer=company.slices&for=job%2Fcadence-design-systems-principal-design-engineer-9"},{"id":"market.stats","title":"A market slice: pay, demand and time to fill","status":"live","price":{"credits":1,"usd":0.1},"unit":"per slice","note":"pay, demand and time to fill for this role and place","call":{"mcp_tool":"market_stats"},"human":"https://alion.io/catalog?offer=market.stats&for=job%2Fcadence-design-systems-principal-design-engineer-9"},{"id":"job.search","title":"Open jobs by role, technology, place, pay and visa","status":"live","price":{"credits":0.02,"usd":0.002},"unit":"per posting in a list","note":"similar open postings","call":{"mcp_tool":"search_jobs"},"human":"https://alion.io/catalog?offer=job.search&for=job%2Fcadence-design-systems-principal-design-engineer-9"},{"id":"company.verify","title":"Is this company real and active right now","status":"pilot","price":null,"unit":"per company","request":{"url":"https://alion.io/catalog/request","method":"POST","body":"{\"offer\": \"company.verify\", \"for\": \"job/cadence-design-systems-principal-design-engineer-9\", \"note\": \"what you need it for\"}"},"human":"https://alion.io/catalog?offer=company.verify&for=job%2Fcadence-design-systems-principal-design-engineer-9"}]}