{"id":3980940,"url":"https://alion.io/job/cadence-design-systems-senior-digital-verification-engineer","title":"Senior Digital Verification Engineer","company":{"id":4351,"name":"Cadence Design Systems","domain":"cadence.com","url":"https://alion.io/company/cadence","size_band":"5000+","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Workday","truth_index":{"grade":"B","score":76,"open_postings":109,"ghost_share":0,"stale_share":0.761,"repost_share":0,"time_to_fill_p50_days":60,"computed_at":"2026-11-10T06:52:35Z"}},"role":"Hardware","role_family":"Hardware","seniority":"senior","employment_type":"full_time","work_mode":"remote","remote_scope":"stated_countries","remote_scope_basis":"posting_text","remote_working_hours":null,"hiring_geo_confidence":"explicit","locations":["Paris, France","France"],"countries":["FR"],"hiring_countries":["FR"],"hiring_countries_total":1,"salary":null,"salary_estimate":null,"experience_years_min":10,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"Cadence Xcelium","optional":false},{"name":"CI/CD","optional":false},{"name":"Formal Verification","optional":false},{"name":"Git","optional":false},{"name":"Python","optional":false},{"name":"SystemVerilog","optional":false},{"name":"UVM","optional":false}],"status":"live","first_seen_at":"2026-11-09T19:42:47Z","employer_posted_date":"2026-11-09","last_verified_at":"2026-11-10T12:42:09Z","board_verified":true,"closed_at":null,"days_open":1,"trust":{"level":"ok","repost_count":null,"flags":[],"days_open":1},"description":"At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.\nCadence is a pivotal leader in electronic design, building upon more than 30 years of computational software expertise. We apply our Intelligent System Design strategy to deliver software, hardware, and IP that turn design concepts into reality.\nThis strategy is supplemented by AI-augmented development practices throughout all our organizations to empower our team to focus on creative problem-solving and innovation. Our customers are the world’s most innovative companies, delivering extraordinary electronic products-from chips to boards to systems-for dynamic market applications including consumer, hyperscale computing, 5G communications, automotive, aerospace, industrial, and health. Join us and be part of a culture that values innovation, collaboration, and customer success.\n\nAt Secure-IC, a Cadence company, we hire and develop leaders and innovators who want to make an impact on the world of technology.\nJob Title: T4 - Principal Design Engineer\n\nLocation: France, Rennes (preferably) or Paris\n\nReports to: Sr Design Engineering Manager\n\nJob Overview:Senior Digital Verification Engineer\nYou will lead the development and execution of robust, reusable UVM verification environments for our products, ensuring functional-coverage and first-silicon success.\nBy driving verification strategy, automating large-scale regression flows, and mentoring the verification team, the role directly safeguards the quality of high-performance ASIC designs.\nThe work spans building scalable test-bench architectures, integrating Cadence verification tools, and collaborating cross-functionally with design and software teams to close verification gaps before RTL freeze.\nJob Responsibilities:\nDefine and implement robust, scalable UVM test-bench architectures for complex digital IPs\nCreate and maintain reusable verification components (sequencers, drivers, monitors, scoreboards, coverage models)\nDevelop directed, random, and constrained-random test cases to achieve 100 % functional coverage and 100 % code coverage on target designs\nLead root-cause analysis of simulation failures, performance bottlenecks, and silicon bring-up bugs\nCoordinate with design teams to close verification gaps before RTL freeze\nContribute to internal verification guidelines, templates, and training materials\nMentor junior verification engineers (T1-T3) and provide technical guidance on UVM, test-bench design, and debugging techniques\nParticipate in design/verification reviews, providing constructive feedback and risk assessment\nJob Qualifications:\nB.S. or M.S. in Electrical Engineering, Computer Engineering, or related field\n7-10 years of professional digital verification experience, including ≥ 5 years with UVM on ASIC or FPGA projects\nProficiency in SystemVerilog/UVM\nStrong hands-on experience with Cadence Xcelium\nKnowledge of synthesis-aware verification (e.g., constraint-driven random verification, coverage-driven closure)\nDeep understanding of functional coverage, assertions (SVA), formal verification, and constrained-random verification\nComfortable with large-scale simulation environments, waveform analysis, and performance profiling\nExcellent communication, problem-solving, and leadership capabilities\nAbility to influence cross-functional teams and mentor junior engineers.\nAdditional Skills/Preferences:\nHands-on with verification IP (VIP) development and integration\nExposure to low-power verification (e.g., power-aware UVM, clock gating checks)\nScripting in Python, TCL, Makefile or Bash for automation\nFamiliarity with Git and CI/CD tools\n\nCheck what we can offer you:\nAn attractive compensation package, including a competitive salary, variable compensation, and meal vouchers\nA positive, stimulating, and supportive work environment\nOffices in France (Rennes and Paris) as well as internationally\nA dynamic and friendly company culture: after-work events, sports challenges, board games, pool table, foosball, and Nintendo Switch\n5 days of paid leave dedicated to volunteering and community engagement, along with 7 “recharge days” (company-wide paid days off)\nThe opportunity to join a company certified Great Place to Work® and ranked among the Fortune 100\nRemote work days\nAccess to a CSE benefits platform, including discounts and gift cards\n\nCadence is committed to equal employment opportunity and employment equity throughout all levels of the organization. We strive to attract a qualified and diverse candidate pool and encourage diversity and inclusion in the workplace.\n***\nCadence est un leader clé dans le domaine de la conception électronique, s’appuyant sur plus de 30 ans d’expertise en logiciels de calcul. Nous appliquons notre stratégie de conception intelligente des systèmes (Intelligent System Design) pour fournir des logiciels, du matériel et des propriétés intellectuelles (IP) qui transforment les concepts de conception en réalité.\nCette stratégie est renforcée par des pratiques de développement augmentées par l’IA au sein de l’ensemble de nos organisations, permettant à nos équipes de se concentrer sur la résolution créative de problèmes et l’innovation. Nos clients comptent parmi les entreprises les plus innovantes au monde, qui conçoivent des produits électroniques exceptionnels - des puces aux cartes, jusqu’aux systèmes - pour des applications de marché dynamiques telles que les produits grand public, l’informatique hyperscale, les communications 5G, l’automobile, l’aéronautique, l’industrie et la santé. Rejoignez-nous et intégrez une culture qui valorise l’innovation, la collaboration et la réussite client.\nChez Secure-IC (Filiale du groupe Cadence), nous recrutons et développons des leaders et des innovateurs désireux d’avoir un impact sur le monde de la technologie.\n\nIntitulé : T4 - Principal Design Engineer\n\nLocalisation : France, Rennes (preferably) or Paris\n\nRattachement hiérarchique : Sr Design Engineering Manager\n\nPrésentation du poste :Senior Digital Verification Engineer\nVous guiderez le développement et l’exécution d’environnements de vérification UVM robustes et réutilisables pour nos produits, garantissant la couverture fonctionnelle et le succès du premier silicium.\nEn pilotant la stratégie de vérification, en automatisant les flux de régression et en encadrant l’équipe de vérification, vous assurerez directement la qualité des conceptions ASIC haute performance.\nLe travail consiste à concevoir des architectures de bancs de test évolutives, à intégrer les outils de vérification Cadence et à collaborer de façon transversale avec les équipes de conception RTL et logicielles les afin de combler les lacunes de vérification avant le « RTL freeze ».\nResponsabilités du poste :\nDéfinir et mettre en œuvre des architectures de bancs de test UVM robustes et évolutives pour des IP numériques complexes\nCréer et maintenir des composants de vérification réutilisables (sequencers, drivers, monitors, scoreboards, coverage models)\nDévelopper des tests dirigés, aléatoires et contraints afin d’atteindre 100 % de couverture fonctionnelle et 100 % de couverture du code sur les produits\nDiriger l’analyse des échecs de simulation, des goulots d’étranglement de performance et des bugs de mise en service du silicium\nCoordonner avec les équipes de conception RTL pour résoudre les lacunes de vérification avant « RTL freeze »\nContribuer aux directives internes de vérification, aux modèles de banc de tests et aux supports de formation\nEncadrer les ingénieurs vérificateurs juniors (T1-T3) et fournir des conseils techniques sur la méthodologie UVM, la conception de bancs de test et les techniques de débogage\nParticiper aux revues de conception/vérification en apportant des retours constructifs et une évaluation des risques\nQualifications requises :\nDiplôme d'ingénieur (Bac+5) ou Master en électronique numérique ou domaine connexe\n7 à 10 ans d’expérience professionnelle en vérification numérique, dont au moins 5 ans avec la méthodologie UVM sur des projets ASIC ou FPGA\nMaîtrise de SystemVerilog et UVM\nUtilisation de Cadence Xcelium.\nConnaissance de la vérification orientée synthèse (ex: vérification aléatoire guidée par contraintes, clôture basée sur la couverture)\nCompréhension approfondie de la couverture fonctionnelle, des assertions (SVA), de la vérification formelle et de la vérification aléatoire sous contraintes (CRV)\nAisance avec les environnements de simulation à grande échelle, l'analyse de chronogrammes (waveforms) et le profilage de performance\nExcellentes capacités de communication, de résolution de problèmes et leadership\nCapacité à influencer des équipes transverses et à encadrer des ingénieurs juniors\nCompétences supplémentaires/Préférences :\nDéveloppement et de l'intégration d'IP de vérification (VIP)\nExpérience en low-power verification (ex: UVM \"power-aware\", vérification du clock gating)\nScripting en Python, TCL, Makefile ou Bash pour l'automatisation\nMaîtrise de Git et des outils CI/CD\n\nDécouvrez ce que nous pouvons vous offrir :\n\nUne rémunération attractive comprenant un salaire compétitif, une part variable et des tickets restaurant\nUn environnement de travail positif, stimulant et bienveillant\nDes bureaux en France (Rennes et Paris) ainsi qu’à l’international\nUne vie d’entreprise dynamique et conviviale : afterworks, défis sportifs, jeux de société, billard, baby-foot, Switch\n5 jours de congés payés dédiés au bénévolat et à l’engagement associatif, ainsi que 7 “recharge days” (jours de repos rémunérés communs à l’ensemble du groupe)\nL’opportunité de rejoindre un groupe certifiée Great Place to Work® et classée Fortune 100\nJours de télétravail\nL’accès à une plateforme d’avantages CSE, incluant réductions et cartes cadeaux\n\nCadence s’engage en faveur de l’égalité des chances et de l’équité en matière d’emploi à tous les niveaux de l’organisation. Nous nous efforçons d’attirer un vivier de candidats qualifiés et diversifiés et de promouvoir la diversité et l’inclusion sur le lieu de travail.\nWe’re doing work that matters. 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