{"id":1207699,"url":"https://alion.io/job/cadence-design-systems-senior-principal-software-engineer","title":"Senior Principal Software Engineer","company":{"id":4351,"name":"Cadence Design Systems","domain":"cadence.com","url":"https://alion.io/company/cadence","size_band":"5000+","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Workday","truth_index":{"grade":"B","score":80,"open_postings":71,"ghost_share":0,"stale_share":0.789,"repost_share":0,"time_to_fill_p50_days":44,"computed_at":"2026-09-25T05:45:01Z"}},"role":"Backend","role_family":"Backend","seniority":"lead","employment_type":"full_time","work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["San Jose, United States"],"countries":["US"],"hiring_countries":[],"hiring_countries_total":0,"salary":{"min":161000,"max":299000,"currency":"USD","period":"year","gross":null,"usd_annual":299000},"salary_estimate":null,"experience_years_min":7,"visa_sponsorship":false,"relocation_package":false,"has_equity":true,"technologies":[{"name":"C++","optional":false},{"name":"Cadence Xcelium","optional":false},{"name":"SystemVerilog","optional":false},{"name":"Verilog","optional":false}],"status":"live","first_seen_at":"2026-09-24T00:00:00Z","employer_posted_date":"2026-09-24","last_verified_at":"2026-09-25T20:18:00Z","board_verified":true,"closed_at":null,"days_open":2,"trust":{"level":"ok","repost_count":null,"flags":[],"days_open":2},"description":"At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.\nJoin the team behind Xcelium, the industry-leading logic simulator, to architect the next generation of hardware verification technology. As a Senior Engineer in the System Verification Group, you will be at the forefront of EDA innovation, evolving the Xcelium simulator to meet the staggering complexity of future AI and hyperscale chip designs. You will be part of an innovative, geographically distributed team dedicated to advancing the capabilities of RTL/logic simulation for semiconductor technology. The work environment encourages collaboration, technical excellence, and continuous learning.\nWe are looking for an experienced C/C++ software engineer to join the Xcelium Software Development Team to develop and enhance RTL/logic simulation products.\nResponsibilities:\nEnhance and support Xcelium RTL/logic simulator engine to add new features and extend existing features.\nEnhance and support Timing Constraints Verification technology used inside Xcelium simulator.\nThe role involves designing, tuning, and innovating graph algorithms involving SDC constraints support on multi-billion-node graphs.\nConduct deep-dive bottleneck analysis and implement performance optimizations in C/C++ to improve compilation speed and memory footprint.\nCollaborate with global team members to deliver high-quality results in a distributed environment.\nWrite Specifications and Unit Tests for your code.\nPosition Requirements/Qualifications:\nMS/PhD in Computer Science or Electrical Engineering.\nMS in Computer Science or Electrical Engineering with a minimum of 7 years of experience OR PhD with a minimum of 5 years of experience\n\n5+ years of experience in EDA software development.\nStrong background in RTL/Logic Simulation, SDC constraints and Timing Analysis especially path exceptions handling in a STA tool.\nExcellent programming skills in C/C++ and a deep understanding of SystemVerilog or Verilog.\nExperience in multi-threaded/ concurrent programming.\nAbility to quickly learn new technologies and adapt to project requirements.\nPrior experience with RTL/logic simulation software development is an added plus.\nThe annual salary range for California is $161,000 to $299,000. You may also be eligible to receive incentive compensation: bonus, equity, and benefits. Sales positions generally offer a competitive On Target Earnings (OTE) incentive compensation structure. Please note that the salary range is a guideline and compensation may vary based on factors such as qualifications, skill level, competencies and work location. Our benefits programs include: paid vacation and paid holidays, 401(k) plan with employer match, employee stock purchase plan, a variety of medical, dental and vision plan options, and more.\nWe’re doing work that matters. Help us solve what others can’t.","description_format":"text","description_chars":2898,"description_truncated":false,"requirements":{"experience_years_min":7,"management_years_min":null,"team_size_min":null,"manages_managers":false,"education":{"level":"master","optional":false},"security_clearance":false,"languages":[]},"benefits":["Continuous learning","Equity"],"hiring_locations":[],"hiring_excludes":[],"relocation_offered":false,"industries":["EDA Software","Semiconductor IP & Chip Design Services"],"lifecycle":[{"event":"open","at":"2026-09-25T01:07:53Z"}],"liveness":{"score":63,"band":"ok","label":"Likely open","p_open":1,"p_active":0.632,"p_room":1,"age_days":1,"expected_fill_days":44,"reasons":["conf:1","stale_co","velocity","win:early","comp:brand"],"computed_at":"2026-09-25T05:45:01Z"},"pay":{"stated_usd_annual":299000,"is_top_pay":true},"html_url":"https://alion.io/job/cadence-design-systems-senior-principal-software-engineer","json_url":"https://alion.io/job/cadence-design-systems-senior-principal-software-engineer.json","meta":{"generated_at":"2026-09-26T02:58:55Z","cache_seconds":300,"methodology":"https://alion.io/methodology","terms":"https://alion.io/terms","contact":"https://alion.io/contact","api":"https://alion.io/developers","usage":{"tier":"crawler","counted_by":"address","units_charged":1,"used_today":3168,"day_limit":5000,"remaining_today":1832,"minute_limit":60,"resets_at":"2026-09-27T00:00:00Z"}}}