{"id":3965407,"url":"https://alion.io/job/cadence-design-systems-software-architect-4","title":"Software Architect","company":{"id":4351,"name":"Cadence Design Systems","domain":"cadence.com","url":"https://alion.io/company/cadence","size_band":"5000+","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Workday","truth_index":{"grade":"B","score":76,"open_postings":108,"ghost_share":0,"stale_share":0.75,"repost_share":0,"time_to_fill_p50_days":60,"computed_at":"2026-11-09T06:03:00Z"}},"role":"Backend","role_family":"Backend","seniority":"staff","employment_type":"full_time","work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Hsinchu, Taiwan"],"countries":["TW"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":null,"experience_years_min":20,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"C++","optional":false}],"status":"live","first_seen_at":"2026-11-09T13:50:12Z","employer_posted_date":"2026-11-09","last_verified_at":"2026-11-09T19:42:47Z","board_verified":true,"closed_at":null,"days_open":0,"trust":{"level":"ok","repost_count":null,"flags":[],"days_open":0},"description":"At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.\nJob Title\nEDA Architect Engineer - Debug, Analysis & FPGA Prototyping\nJob Summary\nWe are seeking a highly experienced Frontend EDA Engineer to lead the development of design debug, analysis, and visualization tools for simulation and emulation solutions. The ideal candidate brings deep technical expertise in large-scale RTL/netlist handling, performance optimization, and customer-driven tool development, with a proven ability to collaborate closely with leading semiconductor and system companies.\nKey Responsibilities\nFrontend Debug & Analysis (Primary Focus)\nArchitect, design, and enhance frontend EDA tools for RTL/gate-level debug, waveform analysis, and design visualization.\nDrive performance, capacity, and usability improvements for large-scale SoC designs.\nEstablish and maintain baseline performance metrics for interactive editing, debugging, and analysis flows.\nLead investigation and resolution of complex customer design issues involving RTL, netlists, timing, and simulation data.\nTechnical Leadership & Customer Engagement\nAct as a technical owner for key frontend initiatives, from concept through deployment.\nPartner closely with tier-1 semiconductor and system customers to deliver high-impact, production-ready solutions.\nProvide technical mentorship to senior and junior engineers across global development teams.\nTranslate customer requirements into clear technical roadmaps and executable plans.\nRequired Qualifications\nMS in Computer Science, Electrical Engineering, or equivalent practical experience.\n20+ years of experience in EDA tool development with strong emphasis on frontend debug/analysis.\nDeep understanding of RTL, netlist, simulation, and verification flows.\nProven experience improving tool performance, scalability, and developer productivity.\nStrong software engineering skills (C/C++, data structures, performance profiling, large-codebase development).\nExperience working directly with customers on complex design and tool-flow challenges.\nPreferred Qualifications\nHands-on experience with Front end design debug platforms.\nBackground in FPGA-based prototyping or emulation systems for SoC validation.\nExperience leading cross-site or multi-disciplinary engineering teams.\nTrack record of delivering order-of-magnitude improvements in performance or productivity.\nPatents or publications related to EDA, debug, or design productivity.\nWe’re doing work that matters. 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