{"id":2080495,"url":"https://alion.io/job/cadence-design-systems-sr-principal-application-engineer-digital-verification","title":"Sr Principal Application Engineer – Digital Verification","company":{"id":4351,"name":"Cadence Design Systems","domain":"cadence.com","url":"https://alion.io/company/cadence","size_band":"5000+","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Workday","truth_index":{"grade":"B","score":82,"open_postings":111,"ghost_share":0,"stale_share":0.73,"repost_share":0,"time_to_fill_p50_days":56,"computed_at":"2026-10-20T05:45:00Z"}},"role":"Hardware","role_family":"Hardware","seniority":"lead","employment_type":"full_time","work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Ho Chi Minh City, Vietnam"],"countries":["VN"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":{"min_usd":25000,"max_usd":57000,"period":"year","method":"global_role_cell_scaled_by_country","sample_n":696},"experience_years_min":10,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"SystemC","optional":false},{"name":"SystemVerilog","optional":false},{"name":"UVM","optional":false},{"name":"Verilog","optional":false},{"name":"VHDL","optional":false}],"status":"closed","first_seen_at":"2026-10-08T10:05:23Z","employer_posted_date":"2026-10-08","last_verified_at":"2026-10-19T19:31:48Z","board_verified":false,"closed_at":"2026-10-19T19:31:48Z","days_open":11,"trust":{"level":"not_scored","repost_count":null,"flags":[],"days_open":11},"description":"At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.\nAct as a tech consultant to lead and support Cadence digital verification solution for customer projects or pre-sales engagements\nWork closely with the sales team to identify, qualify, and scope opportunities for Cadence’s digital functional logic verification solutions.\nUnderstand customer goals and objectives, and plan, execute, and manage key technical evaluations in close collaboration with customers and internal teams.\nProactively engage with existing and prospective customers to ensure successful adoption and deployment of Cadence verification technologies.\nSummarize project activities, status, and outcomes, and report effectively to management while sharing knowledge and best practices within the team.\nTrain, ramp-up and accompany customer project to ensure successful execution and adoption.\nDeliver basic and advanced trainings, technical presentations, and product demonstrations as required.\nProvide deep technical expertise to address complex customer issues and inquiries that require expert-level support.\nRequirements:\nBachelor’s degree or higher in Computer Science, Electrical Engineering, or a related field, with10 + years of relevant industry experience.\n10+ years of hands-on experience and strong expertise in hardware design and/or verification methodologies.\nSolid hands-on verification experience using UVM, SystemVerilog, Verilog, VHDL, SystemC, and SystemVerilog Assertions (SVA).\nHands-on experience with Cadence Verification IP or Jasper is a strong plus.\nGood understanding of code coverage and functional coverage concepts, tools, and technologies.\nStrong communication skills in English, with the ability and motivation to work in a global, customer-facing environment with customers and internal business unit teams.\nValid passport with no travel restrictions; willingness to travel as required.\nWe’re doing work that matters. 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