{"id":3908486,"url":"https://alion.io/job/cadence-design-systems-sr-principal-application-engineer","title":"Sr Principal Application Engineer","company":{"id":4351,"name":"Cadence Design Systems","domain":"cadence.com","url":"https://alion.io/company/cadence","size_band":"5000+","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Workday","truth_index":{"grade":"B","score":76,"open_postings":108,"ghost_share":0,"stale_share":0.75,"repost_share":0,"time_to_fill_p50_days":60,"computed_at":"2026-11-09T06:03:00Z"}},"role":"Industrial Engineering","role_family":"Industrial Engineering","seniority":"lead","employment_type":"full_time","work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["San Jose, United States"],"countries":["US"],"hiring_countries":[],"hiring_countries_total":0,"salary":{"min":148400,"max":275600,"currency":"USD","period":"year","gross":null,"usd_annual":275600},"salary_estimate":null,"experience_years_min":10,"visa_sponsorship":false,"relocation_package":false,"has_equity":true,"technologies":[{"name":"Cadence Conformal","optional":false},{"name":"Perl","optional":false},{"name":"Python","optional":false}],"status":"live","first_seen_at":"2026-11-06T00:00:00Z","employer_posted_date":"2026-11-06","last_verified_at":"2026-11-09T19:42:47Z","board_verified":true,"closed_at":null,"days_open":3,"trust":{"level":"ok","repost_count":null,"flags":[],"days_open":3},"description":"At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.\n\nJob Description\nKey Responsibilities\nHands-on work with Cadence customers in the areas of Backend Digital Design Implementation and Signoff including Synthesis, Place and Route, Design Closure, and timing/power signoff, RTL to GDSII.\nLead technical campaigns and strategies in the RTL to GDSII digital implementation space.\nAggressively push Power, Performance, and Area (PPA)\nDeliver technical presentations and lead discussions internally and with customers.\nWork closely with R&D to enhance the tools and methodologies to meet and exceed customer’s requirements with high quality.\nSupport execution on critical customer flagship product tape outs.\nAmend and augment the flow as needed using Tcl and/or other programming skills to meet objectives and improve results/flows.\nJob Requirements\nMinimum\nMS degree Computer Science/Engineering, Electrical, Engineering, or related field, plus 10+ years industry experience.\nStrong knowledge in Digital Design Fundamentals, Semiconductor fundamentals, and Static Timing Analysis is required.\nPrior experience with IC digital implementation flows and backend EDA tools including Synthesis, Place and Route, IR Drop, backend design timing and power closure, RTL to GDSII.\nExperience in scripting in Perl/Tcl/Python to automate and implement process improvement is a must.\nFloor planning and power planning for System-on-Chip (SoC) designs with low power\nMS degree Computer Science/Engineering, Electrical, Engineering, or related field, plus 10+ years industry experience.\nPrior experience with IC digital implementation flows and front-end EDA tools including Synthesis, DFT, and Logical Equivalence Checking\nGood hands-on experience of Floorplanning, Place and Route, Timing analysis and Sign-off, preferable with CDNS tools suite\nAdvanced clock tree synthesis techniques including SoC Clock Distribution, Clock Mesh, H-Tree\nMultiple design closure including Timing, DRC, LVS, and EMIR preferred.\nExperience with advanced technology nodes including Sub 5nm and below.\nDevelop, debug, and optimize various aspects of design flows for SoC’s to achieve best Power, Performance and Area (PPA)\nStrong customer-facing communication and problem-solving skills\nStrong personal drive for continuous learning and expanding professional skillsets.\nStrong verbal, written, and customer communication skills.\nPrior experience with Cadence tools such as Genus, Innovus, Conformal, Tempus, Modus, and/or Voltus is highly desired.\nThe annual salary range for California is $148,400 to $275,600. You may also be eligible to receive incentive compensation: bonus, equity, and benefits. Sales positions generally offer a competitive On Target Earnings (OTE) incentive compensation structure. Please note that the salary range is a guideline and compensation may vary based on factors such as qualifications, skill level, competencies and work location. Our benefits programs include: paid vacation and paid holidays, 401(k) plan with employer match, employee stock purchase plan, a variety of medical, dental and vision plan options, and more.\nWe’re doing work that matters. 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