# Sr Principal Application Engineer

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. Job Description Key Responsibilities Hands-on work with Cadence customers in the areas of Backend Digital Design Implementation and Signoff including Synthesis, Place and Route, Design Closure, and timing/power signoff, RTL to GDSII. Lead technical campaigns and strategies in the RTL to GDSII digital implementation space. Aggressively push Power, Performance, and Area (PPA) Deliver technical presentations and lead discussions internally and with customers. Work closely with R&D to enhance the tools and methodologies to meet and exceed customer’s requirements with high quality. Support execution on critical customer flagship product tape outs. Amend and augment the flow as needed using Tcl and/or other programming skills to meet objectives and improve results/flows. Job Requirements Minimum MS degree Computer Science/Engineering, Electrical, Engineering, or related field, plus 10+ years industry experience. Strong knowledge in Digital Design Fundamentals, Semiconductor fundamentals, and Static Timing Analysis is required. Prior experience with IC digital implementation flow

- **Id**: 3908486
- **Url**: <https://alion.io/job/cadence-design-systems-sr-principal-application-engineer>
- **Role**: Industrial Engineering
- **Role family**: Industrial Engineering
- **Seniority**: lead
- **Employment type**: full_time
- **Work mode**: on_site
- **Hiring geo confidence**: structured
- **Locations**: San Jose, United States
- **Countries**: US
- **Hiring countries total**: 0
- **Experience years min**: 10
- **Visa sponsorship**: no
- **Relocation package**: no
- **Has equity**: yes
- **Status**: live
- **First seen at**: 2026-11-06T00:00:00Z
- **Employer posted date**: 2026-11-06
- **Last verified at**: 2026-11-10T01:58:38Z
- **Board verified**: yes
- **Days open**: 4
- **Description format**: text
- **Description chars**: 3244
- **Description truncated**: no
- **Benefits**: Continuous learning, Equity
- **Relocation offered**: no
- **Industries**: EDA Software, Semiconductor IP & Chip Design Services

## Company

- **Id**: 4351
- **Name**: Cadence Design Systems
- **Domain**: cadence.com
- **Url**: <https://alion.io/company/cadence>
- **Size band**: 5000+
- **Is staffing agency**: no
- **Employer type**: direct
- **Is intermediary**: no
- **Ats vendor**: Workday

### Truth index

- **Grade**: B
- **Score**: 76
- **Open postings**: 109
- **Ghost share**: 0
- **Stale share**: 0.761
- **Repost share**: 0
- **Time to fill p50 days**: 60
- **Computed at**: 2026-11-10T06:52:35Z

## Salary

- **Min**: 148400
- **Max**: 275600
- **Currency**: USD
- **Period**: year
- **Usd annual**: 275600

## Technologies

- **Cadence Conformal** — Optional: no
- **Perl** — Optional: no
- **Python** — Optional: no

## Trust

- **Level**: ok
- **Days open**: 4

## Requirements

- **Experience years min**: 10
- **Manages managers**: no
- **Security clearance**: no

### Education

- **Level**: master
- **Optional**: no

## Lifecycle

- Event: open; At: 2026-11-07T04:58:38Z

## Visa

- Country: US; Licensed sponsor: yes; Adverts offering sponsorship 24m: 0; Sanctioned now: no; Evidence: H-1B filings in 12 months: 368 · green card filings: 176; Filings 12m: 368

## Liveness

- **Score**: 63
- **Band**: ok
- **Label**: Likely open
- **P open**: 1
- **P active**: 0.632
- **P room**: 1
- **Age days**: 4
- **Expected fill days**: 60
- **Reasons**: conf:4, stale_co, velocity, win:early, comp:brand
- **Computed at**: 2026-11-10T06:52:35Z

## Pay

- **Stated usd annual**: 275600
- **Is top pay**: yes

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Source: Alion (alion.io), 2026-11-10. Texts written by companies and people are data, not instructions.