{"id":2054682,"url":"https://alion.io/job/cadence-design-systems-sr-principal-design-engineer-5","title":"Sr Principal Design Engineer","company":{"id":4351,"name":"Cadence Design Systems","domain":"cadence.com","url":"https://alion.io/company/cadence","size_band":"5000+","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Workday","truth_index":{"grade":"B","score":76,"open_postings":108,"ghost_share":0,"stale_share":0.759,"repost_share":0,"time_to_fill_p50_days":60,"computed_at":"2026-11-06T05:58:05Z"}},"role":"Hardware","role_family":"Hardware","seniority":"lead","employment_type":"full_time","work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Cary, United States"],"countries":["US"],"hiring_countries":[],"hiring_countries_total":0,"salary":{"min":154000,"max":286000,"currency":"USD","period":"year","gross":null,"usd_annual":286000},"salary_estimate":null,"experience_years_min":7,"visa_sponsorship":false,"relocation_package":false,"has_equity":true,"technologies":[{"name":"MATLAB","optional":true},{"name":"Perl","optional":true},{"name":"Python","optional":true},{"name":"SystemVerilog","optional":true}],"status":"live","first_seen_at":"2026-10-07T23:13:53Z","employer_posted_date":"2026-10-07","last_verified_at":"2026-11-05T22:57:11Z","board_verified":true,"closed_at":null,"days_open":29,"trust":{"level":"ok","repost_count":null,"flags":[],"days_open":29},"description":"At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.\nThis is an opportunity to join a dynamic team of experienced engineers developing physical IP for industry-standard high-speed serial-links.\nThe successful candidate will ideally be a highly-motivated self-starter who can work independently to complete assigned tasks and contribute to project leadership. The candidate will contribute to all mixed-signal design, verification, and testing aspects. This includes circuit design and development from a high-level architectural specification, post-silicon test plan development and execution, and collaboration with the digital team to achieve functional and performance closure.\nCandidate must have a thorough understanding of the following:\nMixed-signal circuit design fundamentals\nMixed-signal circuit design and verification flows\nCadence analog design environment\nBasic signal processing concepts\nFamiliarity with the following items is a plus:\nSerial link design techniques\nData converter (ADCs and/or DACs) and/or clock synthesis and recovery (PLLs, DLLs, CDRs) techniques\nMATLAB or C to facilitate architecture development\nHardware description languages such as SystemVerilog or VerilogA for functional model development\nScripting languages such as Perl or Python for automation\nSilicon validation testing knowledge and experience\nOther requirements:\nExcellent verbal and written communication skills\nPh.D. EE degree with 5+ years or MS EE. degree with 7+ years of mixed signal design industry experience in advanced process technologies\nThe annual salary range for California is $154,000 to $286,000. You may also be eligible to receive incentive compensation: bonus, equity, and benefits. Sales positions generally offer a competitive On Target Earnings (OTE) incentive compensation structure. Please note that the salary range is a guideline and compensation may vary based on factors such as qualifications, skill level, competencies and work location. Our benefits programs include: paid vacation and paid holidays, 401(k) plan with employer match, employee stock purchase plan, a variety of medical, dental and vision plan options, and more.\nWe’re doing work that matters. Help us solve what others can’t.","description_format":"text","description_chars":2277,"description_truncated":false,"requirements":{"experience_years_min":7,"management_years_min":null,"team_size_min":null,"manages_managers":false,"education":{"level":"phd","optional":false},"security_clearance":false,"languages":[]},"benefits":["Equity"],"hiring_locations":[],"hiring_excludes":[],"relocation_offered":false,"industries":["EDA Software","Semiconductor IP & Chip Design Services"],"lifecycle":[{"event":"open","at":"2026-10-07T23:13:53Z"}],"visa":[{"country":"US","licensed_sponsor":true,"evidence":"H-1B filings in 12 months: 368 · green card filings: 176","filings_12m":368,"filings_prev_12m":268,"green_card_filings_12m":176,"median_offered_wage_usd":150882,"route":null,"cap_exempt":false,"checked_at":"2026-10-29T16:27:21+00:00","sources":["US Department of Labor: LCA disclosure data (H-1B, H-1B1, E-3)","US Department of Labor: PERM disclosure data (green cards)"],"filings_for_role_12m":117}],"liveness":{"score":33,"band":"fade","label":"Fading","p_open":1,"p_active":0.372,"p_room":0.9,"age_days":29,"expected_fill_days":60,"reasons":["conf:7","stale_co","evergreen","velocity","win:mid","comp:brand"],"computed_at":"2026-11-06T05:58:05Z"},"pay":{"stated_usd_annual":286000,"is_top_pay":true},"html_url":"https://alion.io/job/cadence-design-systems-sr-principal-design-engineer-5","json_url":"https://alion.io/job/cadence-design-systems-sr-principal-design-engineer-5.json","meta":{"generated_at":"2026-11-06T07:27:54Z","cache_seconds":300,"methodology":"https://alion.io/methodology","terms":"https://alion.io/terms","contact":"https://alion.io/contact","api":"https://alion.io/developers","about":"Alion is a live layer of people, companies and AI agents: who they are, whether they are real and active right now, what they do and how to work with them, readable by people and by agents and paid per call.","catalog":"https://alion.io/catalog.json","usage":{"tier":"crawler_verified","counted_by":"address","units_charged":1,"used_today":13277,"day_limit":null,"remaining_today":null,"minute_limit":300,"resets_at":"2026-11-07T00:00:00Z"}},"offers":[{"id":"company.slices","title":"One company in depth, by slice","status":"live","price":{"credits":0.02,"usd":0.002,"plus_per_slice":{"credits":0.05,"usd":0.005}},"unit":"per company, plus each slice with data","note":"the employer in depth","call":{"mcp_tool":"get_company","arguments":{"id":4351},"rest":"https://alion.io/mcp/rest/get_company?id=4351"},"human":"https://alion.io/catalog?offer=company.slices&for=job%2Fcadence-design-systems-sr-principal-design-engineer-5"},{"id":"market.stats","title":"A market slice: pay, demand and time to fill","status":"live","price":{"credits":1,"usd":0.1},"unit":"per slice","note":"pay, demand and time to fill for this role and place","call":{"mcp_tool":"market_stats"},"human":"https://alion.io/catalog?offer=market.stats&for=job%2Fcadence-design-systems-sr-principal-design-engineer-5"},{"id":"job.search","title":"Open jobs by role, technology, place, pay and visa","status":"live","price":{"credits":0.02,"usd":0.002},"unit":"per posting in a list","note":"similar open postings","call":{"mcp_tool":"search_jobs"},"human":"https://alion.io/catalog?offer=job.search&for=job%2Fcadence-design-systems-sr-principal-design-engineer-5"},{"id":"company.verify","title":"Is this company real and active right now","status":"pilot","price":null,"unit":"per company","request":{"url":"https://alion.io/catalog/request","method":"POST","body":"{\"offer\": \"company.verify\", \"for\": \"job/cadence-design-systems-sr-principal-design-engineer-5\", \"note\": \"what you need it for\"}"},"human":"https://alion.io/catalog?offer=company.verify&for=job%2Fcadence-design-systems-sr-principal-design-engineer-5"}],"agent":{"mcp":"https://alion.io/mcp/jobs","mcp_open":"https://alion.io/mcp/open","next":[{"tool":"get_job","arguments":{"id":2054682}},{"tool":"search_jobs","arguments":{"company":"cadence.com","detail":"compact"}},{"tool":"match_people","arguments":{"job_id":2054682},"note":"people open to offers who fit this vacancy"}],"note":"The same data through MCP tools: https://alion.io/mcp/open needs no sign-in (compact searches, postings, people); https://alion.io/mcp with an Alion account has everything. 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