{"id":2870729,"url":"https://alion.io/job/cadence-design-systems-sr-principal-design-engineer-7","title":"Sr Principal Design Engineer","company":{"id":4351,"name":"Cadence Design Systems","domain":"cadence.com","url":"https://alion.io/company/cadence","size_band":"5000+","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Workday","truth_index":{"grade":"B","score":82,"open_postings":114,"ghost_share":0,"stale_share":0.728,"repost_share":0,"time_to_fill_p50_days":57,"computed_at":"2026-10-27T05:46:45Z"}},"role":"Hardware","role_family":"Hardware","seniority":"lead","employment_type":"full_time","work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Bengaluru, India"],"countries":["IN"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":{"min_usd":32000,"max_usd":72000,"period":"year","method":"global_role_cell_scaled_by_country","sample_n":796},"experience_years_min":null,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"Formal Verification","optional":false},{"name":"SystemVerilog","optional":false},{"name":"Verilog","optional":false}],"status":"live","first_seen_at":"2025-09-17T00:00:00Z","employer_posted_date":"2025-09-17","last_verified_at":"2026-10-27T13:34:04Z","board_verified":true,"closed_at":null,"days_open":405,"trust":{"level":"stale","repost_count":0,"flags":["stale"],"days_open":405},"description":"At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.\nJob Summary\nWe are seeking a highly skilled RTL Design Engineer with deep expertise in PCIe protocol (Gen4/Gen5/Gen6) to join our PCIe Controller IP development team. The candidate will be responsible for designing, implementing, and verifying RTL for PCIe controllers and related subsystems, ensuring compliance with protocol standards and performance targets.\nKey Responsibilities\nArchitect and implement RTL for PCIe IP blocks\nCollaborate with system architects to define micro-architecture and design specifications.\nResponsible for the quality of Design Quality. Expertise in LINT/CDC, Synthesis is Must.\nWork closely with verification teams to develop testbenches and validate functionality.\nParticipate in interoperability testing\nContribute to performance, power, and area optimization in advanced nodes.\nInterface with cross-functional teams including PHY, software, and validation.\nRequired Skills\nStrong hands-on experience in RTL design using Verilog/SystemVerilog.\nDeep understanding of PCIe protocol stack and transaction layers.\nExperience with AXI & PXC interfaces, DMA engines, and MSI interrupt handling,\nFamiliarity with CDC design principles and asynchronous FIFO implementation.\nProficiency in synthesis, linting, and static timing analysis.\nExposure to formal verification and assertion-based design methodologies.\nExperience with simulation tools and waveform debugging.\nEducation\nBachelor’s or Master’s degree in Electronics /Electrical Engineering , or related field.\nWe’re doing work that matters. Help us solve what others can’t.","description_format":"text","description_chars":1666,"description_truncated":false,"requirements":{"experience_years_min":null,"management_years_min":null,"team_size_min":null,"manages_managers":false,"education":{"level":"bachelor","optional":false},"security_clearance":false,"languages":[]},"benefits":[],"hiring_locations":[],"hiring_excludes":[],"relocation_offered":false,"industries":["EDA Software","Semiconductor IP & Chip Design Services"],"lifecycle":[{"event":"open","at":"2026-10-19T19:31:48Z"}],"visa":[],"liveness":{"score":3,"band":"cold","label":"Long shot","p_open":1,"p_active":0.115,"p_room":0.28,"age_days":405,"expected_fill_days":57,"reasons":["conf:2","stale_co","evergreen","velocity","win:tail","crowd:brand"],"computed_at":"2026-10-27T05:46:45Z"},"pay":null,"html_url":"https://alion.io/job/cadence-design-systems-sr-principal-design-engineer-7","json_url":"https://alion.io/job/cadence-design-systems-sr-principal-design-engineer-7.json","meta":{"generated_at":"2026-10-27T15:08:37Z","cache_seconds":300,"methodology":"https://alion.io/methodology","terms":"https://alion.io/terms","contact":"https://alion.io/contact","api":"https://alion.io/developers","about":"Alion is a live layer of people, companies and AI agents: who they are, whether they are real and active right now, what they do and how to work with them, readable by people and by agents and paid per call.","catalog":"https://alion.io/catalog.json","usage":{"tier":"crawler_verified","counted_by":"address","units_charged":1,"used_today":4024,"day_limit":null,"remaining_today":null,"minute_limit":300,"resets_at":"2026-10-28T00:00:00Z"}},"offers":[{"id":"company.slices","title":"One company in depth, by slice","status":"live","price":{"credits":0.02,"usd":0.002,"plus_per_slice":{"credits":0.05,"usd":0.005}},"unit":"per company, plus each slice with data","note":"the employer in depth","call":{"mcp_tool":"get_company","arguments":{"id":4351},"rest":"https://alion.io/mcp/rest/get_company?id=4351"},"human":"https://alion.io/catalog?offer=company.slices&for=job%2Fcadence-design-systems-sr-principal-design-engineer-7"},{"id":"market.stats","title":"A market slice: pay, demand and time to fill","status":"live","price":{"credits":1,"usd":0.1},"unit":"per slice","note":"pay, demand and time to fill for this role and place","call":{"mcp_tool":"market_stats"},"human":"https://alion.io/catalog?offer=market.stats&for=job%2Fcadence-design-systems-sr-principal-design-engineer-7"},{"id":"job.search","title":"Open jobs by role, technology, place, pay and visa","status":"live","price":{"credits":0.02,"usd":0.002},"unit":"per posting in a list","note":"similar open postings","call":{"mcp_tool":"search_jobs"},"human":"https://alion.io/catalog?offer=job.search&for=job%2Fcadence-design-systems-sr-principal-design-engineer-7"},{"id":"company.verify","title":"Is this company real and active right now","status":"pilot","price":null,"unit":"per company","request":{"url":"https://alion.io/catalog/request","method":"POST","body":"{\"offer\": \"company.verify\", \"for\": \"job/cadence-design-systems-sr-principal-design-engineer-7\", \"note\": \"what you need it for\"}"},"human":"https://alion.io/catalog?offer=company.verify&for=job%2Fcadence-design-systems-sr-principal-design-engineer-7"}]}