{"id":1160711,"url":"https://alion.io/job/cadence-design-systems-sr-principal-product-engineer-silicon-signoff-verification-ssv-digital-implementation-signoff-solutions","title":"Sr. Principal Product Engineer, Silicon Signoff Verification (SSV) / Digital Implementation & Signoff Solutions","company":{"id":4351,"name":"Cadence Design Systems","domain":"cadence.com","url":"https://alion.io/company/cadence","size_band":"5000+","is_staffing_agency":false,"is_intermediary":false,"listed_via":null,"ats_vendor":"Workday","truth_index":{"grade":"B","score":80,"open_postings":71,"ghost_share":0,"stale_share":0.789,"repost_share":0,"time_to_fill_p50_days":44,"computed_at":"2026-09-24T05:45:00Z"}},"role":"Hardware","role_family":"Hardware","seniority":"lead","employment_type":"full_time","work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Canada"],"countries":["CA"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":{"min_usd":178000,"max_usd":319000,"period":"year","method":"role_seniority_country_remote_cell","sample_n":26},"experience_years_min":12,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"Cadence Innovus","optional":false},{"name":"Cadence Tempus","optional":false},{"name":"Synopsys PrimeTime","optional":false}],"status":"live","first_seen_at":"2026-09-23T23:42:18Z","employer_posted_date":"2026-09-23","last_verified_at":"2026-09-24T03:31:39Z","board_verified":true,"closed_at":null,"days_open":0,"trust":{"level":"ok","repost_count":null,"flags":[],"days_open":0},"description":"At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.\nWe are seeking a Senior Principal Product Engineer (8-12+ years industry experience) to lead advanced signoff methodology development, customer enablement, and product deployment activities for Cadence's timing signoff and ECO solutions. The ideal candidate will possess deep expertise in STA, MMMC signoff, ECO convergence, power optimization, signal integrity, and physical implementation, along with strong customer-facing skills and the ability to influence product direction through close collaboration with R&D and strategic semiconductor customers.\nKey Responsibilities\nDrive development and deployment of advanced signoff methodologies covering timing, power, signal integrity, and ECO closure.\nCollaborate with customers, AE teams, and R&D to resolve complex design closure challenges.\nLead qualification and certification activities for advanced-node design flows.\nDevelop and optimize multi-mode multi-corner (MMMC) timing closure methodologies.\nDrive signoff correlation across implementation, STA, SPICE, and signoff environments.\nDefine and validate methodologies for: Setup and hold closure\nPower optimization\nCrosstalk mitigation\nGlitch fixing\nMax transition and electrical rule fixing\nMulti-view timing closure\n\nSupport customer tapeouts and critical project milestones through root-cause analysis and debug.\nPartner with R&D to prioritize and validate product enhancements and customer-driven requirements.\nCreate deployment collateral, technical presentations, and best-practice methodologies.\nDrive adoption of emerging technologies including AI-assisted signoff and ECO automation.\nRequired Technical Skills\nStrong expertise in Static Timing Analysis (STA)\nMulti-mode multi-corner (MMMC) timing analysis\nSignoff methodologies and timing convergence\nStatistical timing analysis\nSignal Integrity and Crosstalk Analysis\nGlitch analysis and fixing methodologies\nECO implementation and closure flows\nTiming correlation and SPICE correlation\nPower optimization techniques\nBoundary model and hierarchical timing flows\nRC extraction and parasitic analysis\nPhysical implementation and signoff optimization\nDesired Tool Experience\nCadence Tempus/PrimeTime\nCadence Innovus/ICC/FC\nTempus ECO/Tweaker\nPhysical implementation and signoff environments\nAI-assisted design closure workflows\nPreferred Industry Experience\nAdvanced-node ASIC or SoC development\nFoundry qualification and certification programs\nCustomer-facing product engineering\nLarge-scale semiconductor design closure\nTiming, power, and SI signoff methodologies\nLeadership Expectations\nServe as technical lead for strategic customer engagements.\nInfluence product roadmap and methodology direction.\nMentor engineers and drive cross-functional collaboration.\nLead technical reviews and customer escalation management.\nRequired Experience\n8-12+ years of industry experience in semiconductor design, physical implementation, timing signoff, signoff methodology development, or product engineering.\nStrong experience supporting advanced-node SoC/ASIC designs through implementation, timing closure, ECO convergence, and tapeout.\nProven experience working directly with semiconductor customers, R&D organizations, and field engineering teams to resolve complex technical challenges.\nHands-on experience developing and deploying production signoff methodologies across multiple technology nodes and large-scale designs.\nExperience leading technical investigations, driving root-cause analysis, and influencing product enhancements for customer success.\nDemonstrated ability to independently own strategic customer engagements and drive cross-functional execution.\nPreferred Experience\nExperience supporting advanced-node technologies (7nm, 5nm, 3nm, 2nm and beyond).\nExperience with large SoC designs (>100M instance designs) and hierarchical signoff methodologies.\nExperience with power-performance-area (PPA) optimization and signoff closure.\nExperience with customer-facing technical leadership across strategic semiconductor accounts.\nExperience in ECO closure methodologies, signal integrity analysis, glitch fixing, and timing correlation.\nExposure to AI-assisted implementation and signoff workflows is highly desirable.\nWe’re doing work that matters. Help us solve what others can’t.\nWe welcome applications from candidates with disabilities and in equity seeking groups. If you have accessibility needs during the application and interview process, we encourage you to make your needs known.","description_format":"text","description_chars":4575,"description_truncated":false,"requirements":{"experience_years_min":12,"management_years_min":null,"team_size_min":null,"manages_managers":false,"education":null,"security_clearance":false,"languages":[]},"benefits":["Equity"],"hiring_locations":[],"hiring_excludes":[],"relocation_offered":false,"industries":["Wireless"],"lifecycle":[{"event":"open","at":"2026-09-23T23:42:18Z"}],"liveness":{"score":63,"band":"ok","label":"Likely open","p_open":1,"p_active":0.632,"p_room":1,"age_days":0,"expected_fill_days":44,"reasons":["conf:2","stale_co","velocity","win:early","comp:brand"],"computed_at":"2026-09-24T05:45:00Z"},"pay":null,"html_url":"https://alion.io/job/cadence-design-systems-sr-principal-product-engineer-silicon-signoff-verification-ssv-digital-implementation-signoff-solutions","json_url":"https://alion.io/job/cadence-design-systems-sr-principal-product-engineer-silicon-signoff-verification-ssv-digital-implementation-signoff-solutions.json","meta":{"generated_at":"2026-09-24T19:34:27Z","cache_seconds":300,"methodology":"https://alion.io/methodology","terms":"https://alion.io/terms","contact":"https://alion.io/contact","api":"https://alion.io/developers"}}