{"id":1544205,"url":"https://alion.io/job/cadence-design-systems-sr-principal-software-engineer-innovus-physical-synthesis-optimization","title":"Sr Principal Software Engineer, Innovus — Physical Synthesis & Optimization","company":{"id":4351,"name":"Cadence Design Systems","domain":"cadence.com","url":"https://alion.io/company/cadence","size_band":"5000+","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Workday","truth_index":{"grade":"B","score":82,"open_postings":111,"ghost_share":0,"stale_share":0.73,"repost_share":0,"time_to_fill_p50_days":57,"computed_at":"2026-10-30T05:48:23Z"}},"role":"Backend","role_family":"Backend","seniority":"lead","employment_type":"full_time","work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["San Jose, United States"],"countries":["US"],"hiring_countries":[],"hiring_countries_total":0,"salary":{"min":161000,"max":299000,"currency":"USD","period":"year","gross":null,"usd_annual":299000},"salary_estimate":null,"experience_years_min":null,"visa_sponsorship":false,"relocation_package":false,"has_equity":true,"technologies":[{"name":"C++","optional":false},{"name":"CUDA","optional":false},{"name":"HPC","optional":false},{"name":"Linux","optional":false},{"name":"Machine Learning","optional":false},{"name":"Python","optional":false},{"name":"Reinforcement Learning","optional":false}],"status":"live","first_seen_at":"2026-09-30T21:54:09Z","employer_posted_date":"2026-09-30","last_verified_at":"2026-10-30T12:45:31Z","board_verified":true,"closed_at":null,"days_open":29,"trust":{"level":"ok","repost_count":null,"flags":[],"days_open":29},"description":"At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.\nWhy Cadence? - Design for AI. AI for Design.\nCadence sits at the intersection of semiconductor innovation and high-performance computing. Through Design for AI, our EDA technologies enable the advanced silicon platforms powering modern AI infrastructure. Through AI for Design, we integrate machine learning, data-driven optimization, and intelligent automation into our industry-leading implementation flows to transform how chips are designed.\nAs part of the Innovus R&D team, you will build high-performance software engines and algorithms behind next-generation physical synthesis, helping push the boundaries of performance, power, area (PPA), timing closure, and design productivity at scale.\nRole Overview\nWe are looking for a Senior / Staff Software Engineer to contribute to the design and development of next-generation physical synthesis and optimization engines within Innovus.\nIn this hands-on engineering role, you will solve challenging computational problems at the intersection of advanced graph/spatial algorithms, high-performance C++, parallel and distributed computing, and large-scale numerical optimization. Your work will operate at semiconductor scale-where algorithmic efficiency, memory footprint, and multi-core scalability directly impact the ability to design billions of transistors on advanced process nodes.\nKey Responsibilities\nCore Engine & Algorithm DevelopmentDesign, implement, unit-test, and optimize high-performance C++ engines for physical synthesis, placement, and timing-driven optimization.\nDevelop advanced graph algorithms, spatial data structures, and continuous/combinatorial optimization techniques for massive-scale physical design workloads.\nIdentify and eliminate CPU bottlenecks, memory footprint overhead, and algorithmic scaling limits in production C++ codebases.\nTranslate research concepts and mathematical formulations into robust, maintainable, production-quality software.\nParallel & Distributed ComputingImplement multi-threaded and distributed algorithms for computationally intensive implementation engines.\nScale physical design workloads across multi-core systems and compute clusters while minimizing synchronization overhead and memory bandwidth constraints.\nApply modern profiling and benchmarking tools to maximize CPU utilization, cache efficiency, and execution throughput.\nPhysical Design Optimization & R&DDevelop physical design optimization modules addressing timing, power, performance, area (PPA), and congestion.\nWork directly with large-scale layout and netlist data to build practical, highly scalable optimization strategies.\nCollaborate with R&D colleagues to integrate data-driven and AI-assisted optimization heuristics into core synthesis flows.\nQualifications\nRequired Education: Master’s or Ph.D. in Computer Science, Electrical Engineering, Computer Engineering, or a related quantitative field (or equivalent hands-on industry experience).\n C++ Expertise: Strong hands-on experience developing high-performance, production-quality C++ (C++17/20) in Linux environments.\nCore Fundamentals: Solid foundation in data structures, graph algorithms, computational geometry, memory management, and software architecture.\nConcurrent Programming: Practical experience with multithreaded or concurrent programming and low-level performance profiling.\nProblem Solving: Proven ability to analyze, debug, and optimize complex algorithmic bottlenecks in large-scale software systems.\nPreferred EDA / Physical Design: Prior experience developing EDA tools, with specific knowledge in physical synthesis, global/detail placement, static timing analysis (STA), routing, or timing closure.\nAI & Machine Learning: Exposure to applying machine learning, deep learning, reinforcement learning, or data-driven heuristics to software optimization problems.\nScripting & Tooling: Proficiency with Python, Tcl, or shell scripting for benchmarking and workflow automation.\nHPC & Acceleration: Experience with SIMD vectorization, GPU/CUDA acceleration, or large-scale distributed compute frameworks.\nThe Opportunity\nThis role is ideal for a hands-on developer who loves tackling hard algorithmic and systems-level problems at massive scale. Whether your background is rooted deeply in EDA or high-performance systems C++, you will directly write the foundational software engines that power the next generation of global silicon innovation.\nBuild the engines. Scale the algorithms. Shape the future of chip implementation.\nThe annual salary range for California is $161,000 to $299,000. You may also be eligible to receive incentive compensation: bonus, equity, and benefits. Sales positions generally offer a competitive On Target Earnings (OTE) incentive compensation structure. Please note that the salary range is a guideline and compensation may vary based on factors such as qualifications, skill level, competencies and work location. Our benefits programs include: paid vacation and paid holidays, 401(k) plan with employer match, employee stock purchase plan, a variety of medical, dental and vision plan options, and more.\nWe’re doing work that matters. Help us solve what others can’t.","description_format":"text","description_chars":5268,"description_truncated":false,"requirements":{"experience_years_min":null,"management_years_min":null,"team_size_min":null,"manages_managers":false,"education":{"level":"master","optional":false},"security_clearance":false,"languages":[]},"benefits":["Equity"],"hiring_locations":[],"hiring_excludes":[],"relocation_offered":false,"industries":["EDA Software","Semiconductor IP & Chip Design Services"],"lifecycle":[{"event":"open","at":"2026-09-30T21:54:09Z"}],"visa":[{"country":"US","licensed_sponsor":true,"evidence":"H-1B filings in 12 months: 368 · green card filings: 176","filings_12m":368,"filings_prev_12m":268,"green_card_filings_12m":176,"median_offered_wage_usd":150882,"route":null,"cap_exempt":false,"checked_at":"2026-10-29T16:27:21+00:00","sources":["US Department of Labor: LCA disclosure data (H-1B, H-1B1, E-3)","US Department of Labor: PERM disclosure data (green cards)"],"filings_for_role_12m":109}],"liveness":{"score":55,"band":"ok","label":"Likely open","p_open":1,"p_active":0.612,"p_room":0.9,"age_days":29,"expected_fill_days":57,"reasons":["conf:5","stale_co","velocity","win:mid","comp:brand"],"computed_at":"2026-10-30T05:48:23Z"},"pay":{"stated_usd_annual":299000,"is_top_pay":true},"html_url":"https://alion.io/job/cadence-design-systems-sr-principal-software-engineer-innovus-physical-synthesis-optimization","json_url":"https://alion.io/job/cadence-design-systems-sr-principal-software-engineer-innovus-physical-synthesis-optimization.json","meta":{"generated_at":"2026-10-30T17:31:41Z","cache_seconds":300,"methodology":"https://alion.io/methodology","terms":"https://alion.io/terms","contact":"https://alion.io/contact","api":"https://alion.io/developers","about":"Alion is a live layer of people, companies and AI agents: who they are, whether they are real and active right now, what they do and how to work with them, readable by people and by agents and paid per call.","catalog":"https://alion.io/catalog.json","usage":{"tier":"crawler_verified","counted_by":"address","units_charged":1,"used_today":6079,"day_limit":null,"remaining_today":null,"minute_limit":300,"resets_at":"2026-10-31T00:00:00Z"}},"offers":[{"id":"company.slices","title":"One company in depth, by slice","status":"live","price":{"credits":0.02,"usd":0.002,"plus_per_slice":{"credits":0.05,"usd":0.005}},"unit":"per company, plus each slice with data","note":"the employer in depth","call":{"mcp_tool":"get_company","arguments":{"id":4351},"rest":"https://alion.io/mcp/rest/get_company?id=4351"},"human":"https://alion.io/catalog?offer=company.slices&for=job%2Fcadence-design-systems-sr-principal-software-engineer-innovus-physical-synthesis-optimization"},{"id":"market.stats","title":"A market slice: pay, demand and time to fill","status":"live","price":{"credits":1,"usd":0.1},"unit":"per slice","note":"pay, demand and time to fill for this role and place","call":{"mcp_tool":"market_stats"},"human":"https://alion.io/catalog?offer=market.stats&for=job%2Fcadence-design-systems-sr-principal-software-engineer-innovus-physical-synthesis-optimization"},{"id":"job.search","title":"Open jobs by role, technology, place, pay and visa","status":"live","price":{"credits":0.02,"usd":0.002},"unit":"per posting in a list","note":"similar open postings","call":{"mcp_tool":"search_jobs"},"human":"https://alion.io/catalog?offer=job.search&for=job%2Fcadence-design-systems-sr-principal-software-engineer-innovus-physical-synthesis-optimization"},{"id":"company.verify","title":"Is this company real and active right now","status":"pilot","price":null,"unit":"per company","request":{"url":"https://alion.io/catalog/request","method":"POST","body":"{\"offer\": \"company.verify\", \"for\": \"job/cadence-design-systems-sr-principal-software-engineer-innovus-physical-synthesis-optimization\", \"note\": \"what you need it for\"}"},"human":"https://alion.io/catalog?offer=company.verify&for=job%2Fcadence-design-systems-sr-principal-software-engineer-innovus-physical-synthesis-optimization"}],"agent":{"mcp":"https://alion.io/mcp/jobs","mcp_open":"https://alion.io/mcp/open","next":[{"tool":"get_job","arguments":{"id":1544205}},{"tool":"search_jobs","arguments":{"company":"cadence.com","detail":"compact"}},{"tool":"match_people","arguments":{"job_id":1544205},"note":"people open to offers who fit this vacancy"}],"note":"The same data through MCP tools: https://alion.io/mcp/open needs no sign-in (compact searches, postings, people); https://alion.io/mcp with an Alion account has everything. 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