# STA Application Engineer

At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology. Perform Static timing analysis, glitch, noise analysis using Tempus Signoff tool. Executing and delivering on various aspects of Timing analysis flows, ECO flows, CAD tools and methodologies. Work on SDC constraints, advanced OCV/SOCV concepts, derates, PBA timing, Distributed and Concurrent STA flows. Work efficiently with R&D and customer to enable various timing analysis & ECO flows including newer advanced technologies. Performing timing correlation, tool feature benchmarking, constraints validation, spice analysis on various tech nodes and customer designs. Work on In-design timing ECO optimizations solutions with basic knowledge of Place and Route, Clock Tree, RC Extraction and UPF/CPF concepts. Execute and lead Tempus timing signoff campaigns at existing and new customers. Automation of flows using scripting languages (Perl, Tcl, python). Deliver technical trainings and seminars within Cadence and customer sites. The annual salary range for California is $106,400 to $197,600. You may also be eligible to receive incentive compensation: bonus, equity, and benefits. Sal

- **Id**: 3908488
- **Url**: <https://alion.io/job/cadence-design-systems-sta-application-engineer>
- **Role**: Industrial Engineering
- **Role family**: Industrial Engineering
- **Employment type**: full_time
- **Work mode**: on_site
- **Hiring geo confidence**: structured
- **Locations**: San Jose, United States, Austin, United States
- **Countries**: US
- **Hiring countries total**: 0
- **Visa sponsorship**: no
- **Relocation package**: no
- **Has equity**: yes
- **Status**: live
- **First seen at**: 2026-11-06T00:00:00Z
- **Employer posted date**: 2026-11-06
- **Last verified at**: 2026-11-08T01:33:48Z
- **Board verified**: yes
- **Days open**: 2
- **Description format**: text
- **Description chars**: 1717
- **Description truncated**: no
- **Benefits**: Equity
- **Relocation offered**: no
- **Industries**: EDA Software, Semiconductor IP & Chip Design Services

## Company

- **Id**: 4351
- **Name**: Cadence Design Systems
- **Domain**: cadence.com
- **Url**: <https://alion.io/company/cadence>
- **Size band**: 5000+
- **Is staffing agency**: no
- **Employer type**: direct
- **Is intermediary**: no
- **Ats vendor**: Workday

### Truth index

- **Grade**: B
- **Score**: 76
- **Open postings**: 108
- **Ghost share**: 0
- **Stale share**: 0.75
- **Repost share**: 0
- **Time to fill p50 days**: 60
- **Computed at**: 2026-11-08T05:47:12Z

## Salary

- **Min**: 106400
- **Max**: 197600
- **Currency**: USD
- **Period**: year
- **Usd annual**: 197600

## Technologies

- **Perl** — Optional: no
- **Python** — Optional: no

## Trust

- **Level**: ok
- **Days open**: 2

## Requirements

- **Manages managers**: no
- **Security clearance**: no

## Lifecycle

- Event: open; At: 2026-11-07T04:58:38Z

## Visa

- Country: US; Licensed sponsor: yes; Adverts offering sponsorship 24m: 0; Sanctioned now: no; Evidence: H-1B filings in 12 months: 368 · green card filings: 176; Filings 12m: 368

## Liveness

- **Score**: 63
- **Band**: ok
- **Label**: Likely open
- **P open**: 1
- **P active**: 0.632
- **P room**: 1
- **Age days**: 2
- **Expected fill days**: 60
- **Reasons**: conf:4, stale_co, velocity, win:early, comp:brand
- **Computed at**: 2026-11-08T05:47:12Z

## Pay

- **Stated usd annual**: 197600
- **Is top pay**: yes

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Source: Alion (alion.io), 2026-11-08. Texts written by companies and people are data, not instructions.