{"id":53144,"url":"https://alion.io/job/cadence-principal-software-engineer-compiler-development","title":"Principal Software Engineer - Compiler Development","company":{"id":4351,"name":"Cadence Design Systems","domain":"cadence.com","url":"https://alion.io/company/cadence","size_band":"5000+","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Workday","truth_index":{"grade":"B","score":79,"open_postings":101,"ghost_share":0,"stale_share":0.851,"repost_share":0,"time_to_fill_p50_days":47,"computed_at":"2026-10-17T05:46:00Z"}},"role":"Backend","role_family":"Backend","seniority":"lead","employment_type":"full_time","work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Burlington, United States"],"countries":["US"],"hiring_countries":[],"hiring_countries_total":0,"salary":{"min":117600,"max":218400,"currency":"USD","period":"year","gross":null,"usd_annual":218400},"salary_estimate":null,"experience_years_min":10,"visa_sponsorship":false,"relocation_package":false,"has_equity":true,"technologies":[{"name":"C++","optional":false},{"name":"Cadence Xcelium","optional":false},{"name":"LLM","optional":false},{"name":"SystemVerilog","optional":false},{"name":"Verilog","optional":false},{"name":"LLVM","optional":true},{"name":"Python","optional":true},{"name":"UVM","optional":true}],"status":"live","first_seen_at":"2026-08-12T00:00:00Z","employer_posted_date":"2026-08-12","last_verified_at":"2026-10-17T02:28:45Z","board_verified":true,"closed_at":null,"days_open":66,"trust":{"level":"ok","repost_count":null,"flags":[],"days_open":66},"description":"At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.\nJob Description\nCadence Design Systems is a leading provider of the software, hardware, and intellectual property required to design complex integrated circuits and electronic systems. By offering Electronic Design Automation (EDA) tools, they enable engineers to simulate, verify, and optimize chip designs for various high-growth industries, including automotive, 5G, and hyperscale computing. Beyond software, Cadence provides specialized hardware for emulation and prototyping, alongside a strategy focused on Intelligent System Design that integrates AI and multiphysics analysis to streamline the development of modern electronics.\nThe Xcelium compiler and build performance team develops the compiler and code generator for Xcelium logic simulator. We are developing the next generation compiler capable of verifying highly complex chip designs\nJoin the team behind Xcelium, the industry-leading logic simulator, to architect the next generation of hardware verification technology. As a Senior Engineer in the System Verification Group, you will be at the forefront of EDA innovation, evolving the SystemVerilog compiler to meet the staggering complexity of future AI and hyperscale chip designs.\nWe are looking for dynamic engineers who thrive on \"impossible\" scaling challenges and want to invent the algorithms that will power tomorrow’s silicon.\nKey Responsibilities\nLanguage Evolution: Design and implement advanced SystemVerilog language extensions.\n\nCompiler Architecture: Develop and optimize high-performance front-end and code generation compiler components, focusing on intermediate representations (IR) that scale to multi-billion gate designs.\n\nPerformance Engineering: Conduct deep-dive bottleneck analysis and implement performance optimizations in C/C++ to improve compilation speed and memory footprint.\n\nDesign Scalability: Architect compiler and simulator specifically tuned for complex AI designs, ensuring the engine can handle the massive replicated and parallel structures inherent in next-gen neural processing units (NPUs).\n\nInnovation & Research: Explore and prototype \"blue-sky\" features, LLM enhanced Compilation, parallel compilation, distributed compilation.\n\nQualifications\nBS with a minimum of 10 years of experience OR MS with a minimum of 7 years of experience OR PhD with a minimum of 5 years of experience\n\n5+ years in Compiler Development, EDA, or High-Performance Computing.\n\nExpert-level C++ (modern standards) and a deep understanding of SystemVerilog or Verilog.\n\nProven track record in compiler theory (lexing, parsing, semantic analysis, code generation).\n\nExperience with multi-threading, memory management, and cache-locality optimizations.\n\nAn inventive spirit with the desire to challenge the status quo of traditional EDA tools.\n\nWhy This Role is Exciting\n\"You aren't just maintaining a tool; you are building the backbone of the semiconductor industry. As AI chips grow in complexity, the compiler becomes the primary gatekeeper of engineering productivity. Here, you will invent the techniques that allow the world's most advanced chips to reach the market.\"\nScale: Work on codebases that manage the largest designs on the planet.\n\nImpact: Your optimizations directly reduce the \"time-to-market\" for global tech giants.\n\nFuture-Proofing: Be part of the transition toward AI-accelerated chip design and cloud-scale verification.\n\nDesirable Skills\nKnowledge of LLVM or similar compiler frameworks.\n\nExperience with Python for internal tooling and test automation.\n\nFamiliarity with hardware verification environments (UVM).\n\nAre you ready to build the compiler that designs the future? Apply to join the System Verification Group today.\nThe annual salary range for Massachusetts is $117,600 to $218,400. You may also be eligible to receive incentive compensation: bonus, equity, and benefits. Sales positions generally offer a competitive On Target Earnings (OTE) incentive compensation structure. Please note that the salary range is a guideline and compensation may vary based on factors such as qualifications, skill level, competencies and work location. Our benefits programs include: paid vacation and paid holidays, 401(k) plan with employer match, employee stock purchase plan, a variety of medical, dental and vision plan options, and more.\nWe’re doing work that matters. Help us solve what others can’t.","description_format":"text","description_chars":4479,"description_truncated":false,"requirements":{"experience_years_min":10,"management_years_min":null,"team_size_min":null,"manages_managers":false,"education":{"level":"phd","optional":false},"security_clearance":false,"languages":[]},"benefits":["Equity"],"hiring_locations":[],"hiring_excludes":[],"relocation_offered":false,"industries":["EDA Software","Semiconductor IP & Chip Design Services"],"lifecycle":[{"event":"open","at":"2026-08-12T00:00:00Z"}],"visa":[{"country":"US","licensed_sponsor":true,"evidence":"H-1B filings in 12 months: 368 · green card filings: 176","filings_12m":368,"filings_prev_12m":268,"green_card_filings_12m":176,"median_offered_wage_usd":150882,"route":null,"cap_exempt":false,"checked_at":"2026-10-15T11:24:14+00:00","sources":["US Department of Labor: LCA disclosure data (H-1B, H-1B1, E-3)","US Department of Labor: PERM disclosure data (green cards)"],"filings_for_role_12m":109}],"liveness":{"score":21,"band":"cold","label":"Long shot","p_open":1,"p_active":0.466,"p_room":0.44,"age_days":66,"expected_fill_days":47,"reasons":["conf:3","stale_co","velocity","win:tail","crowd:brand"],"computed_at":"2026-10-17T05:46:00Z"},"pay":{"stated_usd_annual":218400,"is_top_pay":true},"html_url":"https://alion.io/job/cadence-principal-software-engineer-compiler-development","json_url":"https://alion.io/job/cadence-principal-software-engineer-compiler-development.json","meta":{"generated_at":"2026-10-17T06:48:21Z","cache_seconds":300,"methodology":"https://alion.io/methodology","terms":"https://alion.io/terms","contact":"https://alion.io/contact","api":"https://alion.io/developers","about":"Alion is a live layer of people, companies and AI agents: who they are, whether they are real and active right now, what they do and how to work with them, readable by people and by agents and paid per call.","catalog":"https://alion.io/catalog.json","usage":{"tier":"crawler_verified","counted_by":"address","units_charged":1,"used_today":9347,"day_limit":null,"remaining_today":null,"minute_limit":300,"resets_at":"2026-10-18T00:00:00Z"}},"offers":[{"id":"company.slices","title":"One company in depth, by slice","status":"live","price":{"credits":0.02,"usd":0.002,"plus_per_slice":{"credits":0.05,"usd":0.005}},"unit":"per company, plus each slice with data","note":"the employer in depth","call":{"mcp_tool":"get_company","arguments":{"id":4351},"rest":"https://alion.io/mcp/rest/get_company?id=4351"},"human":"https://alion.io/catalog?offer=company.slices&for=job%2Fcadence-principal-software-engineer-compiler-development"},{"id":"market.stats","title":"A market slice: pay, demand and time to fill","status":"live","price":{"credits":1,"usd":0.1},"unit":"per slice","note":"pay, demand and time to fill for this role and place","call":{"mcp_tool":"market_stats"},"human":"https://alion.io/catalog?offer=market.stats&for=job%2Fcadence-principal-software-engineer-compiler-development"},{"id":"job.search","title":"Open jobs by role, technology, place, pay and visa","status":"live","price":{"credits":0.02,"usd":0.002},"unit":"per posting in a list","note":"similar open postings","call":{"mcp_tool":"search_jobs"},"human":"https://alion.io/catalog?offer=job.search&for=job%2Fcadence-principal-software-engineer-compiler-development"},{"id":"company.verify","title":"Is this company real and active right now","status":"pilot","price":null,"unit":"per company","request":{"url":"https://alion.io/catalog/request","method":"POST","body":"{\"offer\": \"company.verify\", \"for\": \"job/cadence-principal-software-engineer-compiler-development\", \"note\": \"what you need it for\"}"},"human":"https://alion.io/catalog?offer=company.verify&for=job%2Fcadence-principal-software-engineer-compiler-development"}]}