{"id":161330,"url":"https://alion.io/job/cadence-sr-principal-design-engineer-memory-modeling-portfolio","title":"Sr Principal Design Engineer — Memory Modeling Portfolio","company":{"id":4351,"name":"Cadence Design Systems","domain":"cadence.com","url":"https://alion.io/company/cadence","size_band":"5000+","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Workday","truth_index":{"grade":"B","score":81,"open_postings":110,"ghost_share":0,"stale_share":0.755,"repost_share":0,"time_to_fill_p50_days":57,"computed_at":"2026-11-02T06:13:15Z"}},"role":"Hardware","role_family":"Hardware","seniority":"lead","employment_type":"full_time","work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Shanghai, China"],"countries":["CN"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":{"min_usd":59000,"max_usd":135000,"period":"year","method":"global_role_cell_scaled_by_country","sample_n":796},"experience_years_min":10,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"Cadence Palladium","optional":false},{"name":"Cadence Protium","optional":false},{"name":"Perl","optional":true},{"name":"SystemVerilog","optional":true},{"name":"Verilog","optional":true}],"status":"live","first_seen_at":"2026-08-28T00:00:00Z","employer_posted_date":"2026-08-28","last_verified_at":"2026-11-03T00:48:03Z","board_verified":true,"closed_at":null,"days_open":67,"trust":{"level":"ok","repost_count":null,"flags":[],"days_open":67},"description":"At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.\nOverview:\nThis role sits at the intersection of deep protocol expertise and direct partnership with our customers. As a Design Engineering Architect embedded within Cadence’s Memory Model Portfolio (MMP) R&D team, you will be the primary Korea-based expert for the UFS/Unipro/MPHY/RMMI protocol stack-on the ground with customers, inside their verification challenges, and trusted by the global MMP team to craft solutions as well as to raise the collective expertise of the engineers around you.\nYou will work with leading electronics companies across hyperscale and AI computing, mobile, automotive, and defense/aerospace-helping them deploy, debug, and integrate complex memory protocol IP on our industry-leading Palladium and Protium hardware emulation platforms. This is not a background support role. You are a go-to expert who can fluently read a room, debug an emulation DUT, and translate between the two.\nThe Team\nThe MMP R&D team develops and sustains a world-class memory model IP library spanning UFS/Unipro/MPHY/RMMI, SDRAM families (DDRx, LPDDRx, HBMx), NAND Flash, DFI PHY, and hybrid memory technologies. We are a globally distributed, deeply collaborative group - technically rigorous and genuinely invested in each other’s growth. The culture is one of mutual support, cross-training, and shared ownership of quality. Engineers here become true experts: in protocols, in verification methodology, and in the art of building trust with colleagues and customers. This candidate joins that team as a senior technical anchor in Korea, with visibility across the full global operation.\nResponsibilities:\nServe as the primary customer interface for protocol integration, system-level debugging, and solutions consulting across the UFS/Unipro/MPHY/RMMI stack. Be present and effective on customer sites when the situation calls for it\n\nHelp customers debug, characterize, and articulate the root problem they are trying to solve - even when they don’t yet have the language for it - and translate those findings into clear, actionable problem definitions for the R&D team\n\nTriage and analyze incoming field issues. Scope, disposition, and schedule repair of model defects in close coordination with R&D. Track issues through to resolution with accountability to both the customer and the team\n\nAnalyze customer requirements and map them to MMP product capabilities or feature gaps. Present proposed solutions with clarity to both technical and managerial audiences\n\nMentor and guide less experienced design engineers in protocol understanding, RTL code, and verification methodology. Serve as a reliable senior resource for peers as well as engineers at earlier career stages navigating the emulation and protocol terrain\n\nActively participate in the team’s development lifecycle - reviews, cross-verification, cross-training, quality processes - as a trusted technical contributor, not merely an observer\n\nReview RTL implementation approaches developed by team members; provide technically grounded feedback that raises quality without stalling momentum\n\nPartner with internal account and field teams globally to ensure customer success on complex memory model deployments. Build and sustain long-term, trust-based relationships with key customer contacts\n\nBring consistent energy, stability, and a genuinely collaborative spirit to a team that depends on those qualities as much as on raw technical skill\n\nJob Qualifications:\nRequired:\nMaster’s degree in Electrical Engineering or equivalent with 10+ years of relevant industry experience, or PhD with 8+ years\n\nDeep, demonstrable expertise in the full UFS/Unipro/MPHY/RMMI protocol stack - knowledge broad enough to debug across layers and precise enough to pinpoint root cause efficiently; this is a hard requirement, not a nice-to-have\n\nFluent in SystemVerilog/Verilog RTL design and verification. Able to write, review, and rigorously debug RTL constructs as used in hardware emulation environments\n\nAdvanced English written and verbal fluency - essential for a globally integrated team whose communication runs through English at every level\n\nProven debugging skill and the discipline to stay methodical, patient, and precise under customer pressure\n\nEmotionally intelligent; a natural collaborator who brings steadiness, genuine curiosity, and a real interest in the people across the table - customers and teammates alike\n\nStrongly Preferred:\nHands-on experience with Cadence Palladium and/or Protium emulation platforms\n\nFamiliarity with scripting environments (Perl, TCL, C-shell)\n\nBreadth of protocol exposure beyond UFS - SDRAM families, NAND Flash, or other complex communication protocols - enough to consult credibly across our wider MMP team\n\nExperience navigating diverse customer behavioral styles across cultures and building trusted, long-term technical relationships\n\nWe’re doing work that matters. Help us solve what others can’t.","description_format":"text","description_chars":5026,"description_truncated":false,"requirements":{"experience_years_min":10,"management_years_min":null,"team_size_min":null,"manages_managers":false,"education":{"level":"master","optional":true},"security_clearance":false,"languages":[{"language":"English","level":"Advanced (C1)","optional":false}]},"benefits":[],"hiring_locations":[],"hiring_excludes":[],"relocation_offered":false,"industries":["EDA Software","Semiconductor IP & Chip Design Services"],"lifecycle":[{"event":"open","at":"2026-08-28T00:00:00Z"}],"visa":[],"liveness":{"score":32,"band":"fade","label":"Fading","p_open":1,"p_active":0.58,"p_room":0.55,"age_days":66,"expected_fill_days":57,"reasons":["conf:0","stale_co","velocity","win:tail","comp:brand"],"computed_at":"2026-11-02T06:13:15Z"},"pay":null,"html_url":"https://alion.io/job/cadence-sr-principal-design-engineer-memory-modeling-portfolio","json_url":"https://alion.io/job/cadence-sr-principal-design-engineer-memory-modeling-portfolio.json","meta":{"generated_at":"2026-11-03T02:49:28Z","cache_seconds":300,"methodology":"https://alion.io/methodology","terms":"https://alion.io/terms","contact":"https://alion.io/contact","api":"https://alion.io/developers","about":"Alion is a live layer of people, companies and AI agents: who they are, whether they are real and active right now, what they do and how to work with them, readable by people and by agents and paid per call.","catalog":"https://alion.io/catalog.json","usage":{"tier":"crawler_verified","counted_by":"address","units_charged":1,"used_today":3716,"day_limit":null,"remaining_today":null,"minute_limit":300,"resets_at":"2026-11-04T00:00:00Z"}},"offers":[{"id":"company.slices","title":"One company in depth, by slice","status":"live","price":{"credits":0.02,"usd":0.002,"plus_per_slice":{"credits":0.05,"usd":0.005}},"unit":"per company, plus each slice with data","note":"the employer in depth","call":{"mcp_tool":"get_company","arguments":{"id":4351},"rest":"https://alion.io/mcp/rest/get_company?id=4351"},"human":"https://alion.io/catalog?offer=company.slices&for=job%2Fcadence-sr-principal-design-engineer-memory-modeling-portfolio"},{"id":"market.stats","title":"A market slice: pay, demand and time to fill","status":"live","price":{"credits":1,"usd":0.1},"unit":"per slice","note":"pay, demand and time to fill for this role and place","call":{"mcp_tool":"market_stats"},"human":"https://alion.io/catalog?offer=market.stats&for=job%2Fcadence-sr-principal-design-engineer-memory-modeling-portfolio"},{"id":"job.search","title":"Open jobs by role, technology, place, pay and visa","status":"live","price":{"credits":0.02,"usd":0.002},"unit":"per posting in a list","note":"similar open postings","call":{"mcp_tool":"search_jobs"},"human":"https://alion.io/catalog?offer=job.search&for=job%2Fcadence-sr-principal-design-engineer-memory-modeling-portfolio"},{"id":"company.verify","title":"Is this company real and active right now","status":"pilot","price":null,"unit":"per company","request":{"url":"https://alion.io/catalog/request","method":"POST","body":"{\"offer\": \"company.verify\", \"for\": \"job/cadence-sr-principal-design-engineer-memory-modeling-portfolio\", \"note\": \"what you need it for\"}"},"human":"https://alion.io/catalog?offer=company.verify&for=job%2Fcadence-sr-principal-design-engineer-memory-modeling-portfolio"}],"agent":{"mcp":"https://alion.io/mcp/jobs","mcp_open":"https://alion.io/mcp/open","next":[{"tool":"get_job","arguments":{"id":161330}},{"tool":"search_jobs","arguments":{"company":"cadence.com","detail":"compact"}},{"tool":"match_people","arguments":{"job_id":161330},"note":"people open to offers who fit this vacancy"}],"note":"The same data through MCP tools: https://alion.io/mcp/open needs no sign-in (compact searches, postings, people); https://alion.io/mcp with an Alion account has everything. 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