{"id":53151,"url":"https://alion.io/job/cadence-sr-principal-design-engineer","title":"Sr. Principal Design Engineer","company":{"id":4351,"name":"Cadence Design Systems","domain":"cadence.com","url":"https://alion.io/company/cadence","size_band":"5000+","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Workday","truth_index":{"grade":"B","score":80,"open_postings":104,"ghost_share":0,"stale_share":0.817,"repost_share":0,"time_to_fill_p50_days":47,"computed_at":"2026-10-12T06:55:09Z"}},"role":"Industrial Engineering","role_family":"Industrial Engineering","seniority":"lead","employment_type":"full_time","work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Hyderabad, India"],"countries":["IN"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":null,"experience_years_min":6,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"Cadence Virtuoso","optional":false},{"name":"Perl","optional":false},{"name":"Python","optional":false}],"status":"closed","first_seen_at":"2026-08-10T00:00:00Z","employer_posted_date":"2026-08-10","last_verified_at":"2026-09-30T21:54:09Z","board_verified":false,"closed_at":"2026-09-30T21:54:09Z","days_open":51,"trust":{"level":"not_scored","repost_count":null,"flags":[],"days_open":51},"description":"At Cadence, we hire and develop leaders and innovators who want to make an impact on the world of technology.\n1. Role Overview & Objective\nWe are looking for a motivated SRAM Circuit Design Engineer to join our semiconductor engineering team developing circuits and SRAM/Register File for low power, low voltage and high performance.\nThis role is ideal for candidates who are passionate about memory design, characterization methodologies, and physical verification, and who are eager to build a strong foundation in VLSI memory development.\n2. Key Responsibilities\nCircuit Design & Optimization: Build full-custom or compiler-based SRAM macros, sense amplifiers, and self-timed circuits.\n Simulation & Characterization: Run SPICE simulations to analyze timing, power, and Static Noise Margin (SNM) across process corners.\nLayout Supervision: Direct physical design and layout teams to handle process variability and FinFET manufacturing rules.\nSilicon Validation & Debug: Support post-silicon testing and troubleshooting hardware failures\n3. Required Qualifications & Experience\nEducation: B.Tech/M.Tech in Electrical Engineering, VLSI, or Microelectronics.\nExperience: Typically ranges from 6 to 18 years depending on whether the role is entry/mid-level or a senior lead/architect position.\nCore Knowledge: Deep understanding of CMOS device physics, transistor sizing, and memory cell stability.\nTools: Proficiency in EDA software like Cadence Virtuoso or SPICE simulators.\nScripting: Ability to use Python or Perl for workflow automation and data analysis\n4. Behavioral & Soft Skills\nStrong analytical and problem-solving skills.\nHigh attention to detail.\nAbility to collaborate cross-functionally with circuit designers, architecture teams, and CAD engineers.\nWe’re doing work that matters. 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