{"id":2418751,"url":"https://alion.io/job/cai-design-verification-engineer","title":"Design Verification Engineer","company":{"id":1819291,"name":"CAI","domain":"cai.io","url":"https://alion.io/company/cai-io","size_band":null,"is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Workday","truth_index":{"grade":"B","score":75,"open_postings":10,"ghost_share":0,"stale_share":1,"repost_share":0,"time_to_fill_p50_days":null,"computed_at":"2026-10-13T05:45:00Z"}},"role":"Hardware","role_family":"Hardware","seniority":"junior","employment_type":"full_time","work_mode":"remote","remote_scope":"stated_countries","remote_scope_basis":"board_field","remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Manila, Philippines"],"countries":["PH"],"hiring_countries":["PH"],"hiring_countries_total":1,"salary":null,"salary_estimate":{"min_usd":15000,"max_usd":37000,"period":"year","method":"global_role_cell_scaled_by_country","sample_n":621},"experience_years_min":2,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"Perl","optional":false},{"name":"Python","optional":false},{"name":"SystemVerilog","optional":false},{"name":"UVM","optional":false},{"name":"Verilog","optional":false}],"status":"live","first_seen_at":"2026-10-13T04:26:19Z","employer_posted_date":"2026-10-13","last_verified_at":"2026-10-13T05:17:54Z","board_verified":true,"closed_at":null,"days_open":0,"trust":{"level":"ok","repost_count":null,"flags":[],"days_open":0},"description":"Design Verification EngineerReq number:\nR8709Employment type:\nFull timeWorksite flexibility:\nRemoteWho we are\nCAI is a global services firm with over 9,000 associates worldwide and a yearly revenue of $1.3 billion+. We have over 40 years of excellence in uniting talent and technology to power the possible for our clients, colleagues, and communities. As a privately held company, we have the freedom and focus to do what is right-whatever it takes. Our tailor-made solutions create lasting results across the public and commercial sectors, and we are trailblazers in bringing neurodiversity to the enterprise.\nJob Summary\nAs a Design Verification Engineer, you will develop test benches and perform design verification of mixed-signal products prior to tape-out. You'll create advanced environments that support comprehensive, metric-driven verification processes and ensure the accuracy and reliability of designs through code coverage analysis. Working with moderate supervision, you'll collaborate with cross-functional teams to meet project timelines and quality standards, applying your technical expertise to solve verification challenges.Job Description\nWe are looking for an experienced Design Verification Engineer to develop and execute comprehensive test benches for mixed-signal product verification using SystemVerilog and UVM methodologies. This position is full-time and remote.\nWhat You'll Do\nDevelop and execute comprehensive test benches for mixed-signal product verification using SystemVerilog and UVM methodologies \nCreate and maintain verification plans, focusing on functional and code coverage metrics to ensure design quality \nDebug verification issues using advanced troubleshooting techniques and provide effective solutions \nCollaborate with design teams to align verification strategies with project requirements \nCreate and maintain detailed documentation for verification processes and results \nParticipate in design reviews and provide verification insights to improve overall product quality \nApply scripting skills and use AI tools to automate verification tasks and improve efficiency \nWhat You'll Need\nRequired:\nBachelor’s or Master’s degree in electrical engineering, Electronics and Communications Engineering, Computer Engineering, or related field \n2 to 4 years of relevant experience in digital design verification\nSystemVerilog & UVM: Proficiency in developing and maintaining verification environments using SystemVerilog and Universal Verification Methodology for complex designs \nTest Bench Development: Ability to develop comprehensive test benches for mixed-signal product verification, focusing on coverage-driven methodologies \nScripting: Capability to create and implement automation scripts using Python, Perl, or TCL to enhance verification workflows \nVerilog RTL: Strong understanding of Register Transfer Level design concepts and their application in verification \nEDA Tools: Experience with electronic design automation tools and simulators for effective design verification \nDebugging: Demonstrated ability to analyze and resolve moderately complex verification issues with limited supervision\nPhysical Demands\nAbility to safely and successfully perform the essential job functions \nSedentary work that involves sitting or remaining stationary most of the time, with occasional need to move around the office to attend meetings, etc. \nAbility to conduct repetitive tasks on a computer, utilizing a mouse, keyboard, and monitor\nReasonable accommodation statement\nIf you require a reasonable accommodation in completing this application, interviewing, completing any pre-employment testing, or otherwise participating in the employment selection process, please direct your inquiries to  (888) 824 - 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