{"id":4065223,"url":"https://alion.io/job/canaan-xiaozhao-kitajing-rtl-design-engineer-memory-interconnect","title":"校招 北京-RTL Design Engineer (Memory & Interconnect)","company":{"id":47567,"name":"Canaan","domain":"canaan.io","url":"https://alion.io/company/canaan","size_band":null,"is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Beisen","truth_index":null},"role":"Hardware","role_family":"Hardware","seniority":"junior","employment_type":null,"work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Beijing, China"],"countries":["CN"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":null,"experience_years_min":null,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"SystemVerilog","optional":false},{"name":"Verilog","optional":false},{"name":"AI Agents","optional":true}],"status":"live","first_seen_at":"2026-11-11T10:56:54Z","employer_posted_date":"2026-11-11","last_verified_at":"2026-11-12T09:06:35Z","board_verified":true,"closed_at":null,"days_open":1,"trust":{"level":"ok","repost_count":null,"flags":[],"days_open":1},"description":"岗位职责 / Responsibilities\nCore Responsibilities\nUse AI tools across the digital IC front-end flow; integrate automated agents into design flows and continuously optimize.\nDrive microarchitecture design, iteration, and RTL implementation for memory subsystems and data movement.\nPerform functional evaluation and performance analysis; support pre-simulation verification.\n任职要求 / Requirements\nRequirements\nMaster’s or above in Electronics, Computer Science, or related fields.\nBasic Verilog/SystemVerilog and digital circuit fundamentals.\nNo prior experience required; digital IC project experience is a plus. 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