{"id":1808469,"url":"https://alion.io/job/capgemini-dft-engineer-2","title":"DFT Engineer","company":{"id":145,"name":"Capgemini","domain":"capgemini.com","url":"https://alion.io/company/capgemini","size_band":"5000+","is_staffing_agency":false,"employer_type":"services","is_intermediary":false,"listed_via":null,"ats_vendor":"Career site","truth_index":{"grade":"B","score":75,"open_postings":915,"ghost_share":0,"stale_share":1,"repost_share":0,"time_to_fill_p50_days":23,"computed_at":"2026-10-04T05:45:00Z"}},"role":"Industrial Engineering","role_family":"Industrial Engineering","seniority":"staff","employment_type":"full_time","work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Bengaluru, India"],"countries":["IN"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":{"min_usd":22000,"max_usd":50000,"period":"year","method":"global_role_cell_scaled_by_country","sample_n":944},"experience_years_min":12,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"Tessent","optional":false}],"status":"live","first_seen_at":"2026-09-10T10:34:51Z","employer_posted_date":"2026-09-10","last_verified_at":"2026-10-05T02:32:09Z","board_verified":true,"closed_at":null,"days_open":24,"trust":{"level":"ok","repost_count":null,"flags":[],"days_open":24},"description":"Job Description\nLead DFT architecture and test strategy definition for advanced SoCs, ensuring high-quality manufacturing testability and diagnosis readiness.\nJob Description - Grade Specific\nKey Responsibilities\nDefine SoC DFT architecture.\nEstablish ATPG, scan, MBIST, LBIST strategies.\nDrive test coverage objectives.\nDefine compression and diagnosis methodologies.\nWork with RTL, Verification, and Physical Design teams.\nReview DFT signoff requirements.\nInterface with customer test and manufacturing organizations.\nMust Have\n12+ years of DFT experience.\nMultiple successful SoC tapeouts.\nGood Knowledge on RISC and ARM SoC DFT strategy for sub-systems and top level\nExpertise in scan insertion and ATPG.\nStrong understanding of MBIST/LBIST.\nExperience with Tessent and/or Synopsys DFT tools.\nKnowledge of test compression and diagnosis.\nUnderstanding of JTAG and IEEE 1500/1687.\nGood to Have\nSafety DFT.\nAutomotive test methodologies.\nSilicon bring-up support experience.\nYield learning and diagnosis.\nChiplet test architecture.\nAdvanced node test challenges.","description_format":"text","description_chars":1064,"description_truncated":false,"requirements":{"experience_years_min":12,"management_years_min":null,"team_size_min":null,"manages_managers":false,"education":null,"security_clearance":false,"languages":[]},"benefits":[],"hiring_locations":[],"hiring_excludes":[],"relocation_offered":false,"industries":["Cybersecurity","Government","Science & Engineering","Research Institutes"],"lifecycle":[{"event":"open","at":"2026-10-03T19:42:35Z"}],"visa":[],"liveness":{"score":29,"band":"fade","label":"Fading","p_open":1,"p_active":0.53,"p_room":0.55,"age_days":23,"expected_fill_days":23,"reasons":["conf:0","stale_co","velocity","win:tail","comp:brand"],"computed_at":"2026-10-04T05:45:00Z"},"pay":null,"html_url":"https://alion.io/job/capgemini-dft-engineer-2","json_url":"https://alion.io/job/capgemini-dft-engineer-2.json","meta":{"generated_at":"2026-10-05T03:22:17Z","cache_seconds":300,"methodology":"https://alion.io/methodology","terms":"https://alion.io/terms","contact":"https://alion.io/contact","api":"https://alion.io/developers","usage":{"tier":"crawler","counted_by":"address","units_charged":1,"used_today":4516,"day_limit":5000,"remaining_today":484,"minute_limit":60,"resets_at":"2026-10-06T00:00:00Z"}}}