{"id":1798571,"url":"https://alion.io/job/capgemini-physical-design-engineer","title":"Physical Design Engineer","company":{"id":145,"name":"Capgemini","domain":"capgemini.com","url":"https://alion.io/company/capgemini","size_band":"5000+","is_staffing_agency":false,"employer_type":"services","is_intermediary":false,"listed_via":null,"ats_vendor":"Career site","truth_index":{"grade":"B","score":75,"open_postings":915,"ghost_share":0,"stale_share":1,"repost_share":0,"time_to_fill_p50_days":23,"computed_at":"2026-10-04T05:45:00Z"}},"role":"Industrial Engineering","role_family":"Industrial Engineering","seniority":"senior","employment_type":"full_time","work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Ukraine"],"countries":["UA"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":{"min_usd":35000,"max_usd":78000,"period":"year","method":"global_role_cell_scaled_by_country","sample_n":3947},"experience_years_min":5,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"Perl","optional":true},{"name":"Python","optional":true},{"name":"Synopsys Fusion Compiler","optional":true}],"status":"live","first_seen_at":"2026-01-22T14:57:24Z","employer_posted_date":"2026-10-03","last_verified_at":"2026-10-05T02:32:09Z","board_verified":true,"closed_at":null,"days_open":255,"trust":{"level":"stale","repost_count":0,"flags":["stale"],"days_open":254},"description":"At Capgemini Engineering, the world leader in engineering services, we bring together a global team of engineers, scientists, and architects to help the world’s most innovative companies unleash their potential. From autonomous cars to life-saving robots, our digital and software technology experts think outside the box as they provide unique R&D and engineering services across all industries. Join us for a career full of opportunities. Where you can make a difference. Where no two days are the same.\nJob Description:\nAre you in search for a new challenge? Are you equipped with forward thinking spirit and experienced in digital design flows and tools? Physical Design has a multi-lateral spectrum of increasing complexity which involves deep understanding of cutting-edge designs and technologies, methods, tools, development and implementation flows. Take the opportunity and join us as a Senior Physical Design Engineer.\nPresently we expand our Ukraine VLSI team. You'd be able to work on projects in one team with Ukrainian engineers. Our Senior stuff is open for knowledge sharing on a daily basis.\nJob Responsibilities:\nResponsible for all aspects of Physical Design in full chip or block level in extremely advanced technologies nodes (10nm and below);\nIn deep Floorplanning, partitioning/budgeting, power mesh distribution, clock tree planning and analysis, Scan re-ordering, placement, CTS, place and route;\nCover all relevant activities related to timing analysis (closure through sign-off including SI/noise) ECO tasks (both functional and timing);\nIn charge with all validation/qualification tasks: Formal Verification, EM/IR, DRC, LVS, Antenna, ERC analysis and fixes;\nBe part of the overall Low Power solution development and implementation;\nDevelop/enhance timing related scripts for clock skew analysis, critical path analysis, various IO interfaces, constraints partitioning/budgeting (from top-level to block level);\nComplete multiple design cycles of high complexity with little supervision.\nDesired Qualifications:\n5+ years (desirable) in challenging RTL2GDSII work done on 10nm or below nodes with 500k - 1million+ instances in designs;\nPower user of PnR and timing analysis CAD tools from Synopsys and/or Cadence;\nGood knowledge of synthesis flow, insertDFT scan/coverage and optimization;\nExcellent floorplan, power plan, CTS, place, route, and timing closure skills;\nProficiency using Perl/TCL/Python scripting and Makefile;\nExpertise in timing STA/PTSI - signal integrity closure, ECO generation/implementation skill;\nExcellent EM/IR, DRC, LVS, ERC analysis and fixing skills;\nExperience with sign-off tape-out closure work;\nAny top level - floor planning, pin assignment - tape out activities is a plus.\nSkills:\nSynthsesis, SDC constraints, Static timing analysis (STA), STA signoff, Partitioning constraints, UPF constraints, low power modes, power islands, PVT corners, EDA tools. EDA tools: DC compiler, Fusion compiler, Cadence tools, Siemens tools.\nWhat you will love about working here?\nWe care about all our employees and want them to feel as comfortable as possible. That's why we offer health insurance from the first days, regardless of the probationary period.\nThe Gift from the Company - Christmas holidays from December 25 to December 31.\nCooperation with Superhumans center and Veteran HUB. Capgemini Engineering has supported the launch of psychological rehabilitation department of Superhumans. Our team also donated over UAH 500 000 prosthetics for three Ukrainian defenders. Currently, we support psychological counseling provided by the Veteran Hub, and we have implemented an internal policy making the company friendly to military and veterans with the assistance of the Hub.\nCapgemini is a global business and technology transformation partner, helping organizations to accelerate their dual transition to a digital and sustainable world, while creating tangible impact for enterprises and society. It is a responsible and diverse group of 340,000 team members in more than 50 countries. With its strong over 55-year heritage, Capgemini is trusted by its clients to unlock the value of technology to address the entire breadth of their business needs. It delivers end-to-end services and solutions leveraging strengths from strategy and design to engineering, all fueled by its market leading capabilities in AI, generative AI, cloud and data, combined with its deep industry expertise and partner ecosystem.","description_format":"text","description_chars":4462,"description_truncated":false,"requirements":{"experience_years_min":5,"management_years_min":null,"team_size_min":null,"manages_managers":false,"education":null,"security_clearance":false,"languages":[]},"benefits":["Health insurance"],"hiring_locations":[],"hiring_excludes":[],"relocation_offered":false,"industries":["Cybersecurity","Government","Science & Engineering","Research Institutes"],"lifecycle":[{"event":"open","at":"2026-10-03T18:22:42Z"}],"visa":[{"country":"US","licensed_sponsor":true,"evidence":"H-1B filings in 12 months: 2,076 · green card filings: 82","filings_12m":2076,"filings_prev_12m":2803,"green_card_filings_12m":82,"median_offered_wage_usd":132120,"route":null,"cap_exempt":false,"checked_at":"2026-10-03T21:08:04+00:00","sources":["US Department of Labor: LCA disclosure data (H-1B, H-1B1, E-3)","US Department of Labor: PERM disclosure data (green cards)"],"filings_for_role_12m":0},{"country":"CA","licensed_sponsor":true,"evidence":"Positions approved through LMIA in 12 months: 11","filings_12m":11,"filings_prev_12m":10,"green_card_filings_12m":null,"median_offered_wage_usd":null,"route":"Global Talent Stream; High Wage","cap_exempt":false,"checked_at":"2026-10-03T21:10:52+00:00","sources":["ESDC: employers issued a positive LMIA"],"filings_for_role_12m":0},{"country":"GB","licensed_sponsor":true,"evidence":"Licensed UK visa sponsor (Graduate Trainee, Skilled Worker, Senior or Specialist Worker)","filings_12m":null,"filings_prev_12m":null,"green_card_filings_12m":null,"median_offered_wage_usd":null,"route":"Global Business Mobility: Graduate Trainee; Skilled Worker; Global Business Mobility: Senior or Specialist Worker","cap_exempt":false,"checked_at":"2026-10-03T21:09:13+00:00","sources":["UK Home Office: register of licensed sponsors (workers)"],"filings_for_role_12m":0}],"liveness":{"score":5,"band":"cold","label":"Long shot","p_open":1,"p_active":0.161,"p_room":0.28,"age_days":254,"expected_fill_days":23,"reasons":["conf:0","stale_co","velocity","win:tail","crowd:brand"],"computed_at":"2026-10-04T05:45:00Z"},"pay":null,"html_url":"https://alion.io/job/capgemini-physical-design-engineer","json_url":"https://alion.io/job/capgemini-physical-design-engineer.json","meta":{"generated_at":"2026-10-05T03:26:53Z","cache_seconds":300,"methodology":"https://alion.io/methodology","terms":"https://alion.io/terms","contact":"https://alion.io/contact","api":"https://alion.io/developers","usage":{"tier":"crawler","counted_by":"address","units_charged":1,"used_today":4610,"day_limit":5000,"remaining_today":390,"minute_limit":60,"resets_at":"2026-10-06T00:00:00Z"}}}