{"id":1806024,"url":"https://alion.io/job/capgemini-rf-analog-layout-engineer-2","title":"RF Analog Layout Engineer","company":{"id":145,"name":"Capgemini","domain":"capgemini.com","url":"https://alion.io/company/capgemini","size_band":"5000+","is_staffing_agency":false,"employer_type":"services","is_intermediary":false,"listed_via":null,"ats_vendor":"Career site","truth_index":{"grade":"B","score":81,"open_postings":1720,"ghost_share":0,"stale_share":0.757,"repost_share":0.001,"time_to_fill_p50_days":27,"computed_at":"2026-10-10T05:45:15Z"}},"role":"Hardware","role_family":"Hardware","seniority":null,"employment_type":"full_time","work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Niš, Serbia"],"countries":["RS"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":{"min_usd":29000,"max_usd":87000,"period":"year","method":null,"sample_n":3534},"experience_years_min":null,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[],"status":"live","first_seen_at":"2026-09-11T14:42:46Z","employer_posted_date":"2026-09-22","last_verified_at":"2026-10-11T01:27:19Z","board_verified":true,"closed_at":null,"days_open":29,"trust":{"level":"ok","repost_count":null,"flags":[],"days_open":29},"description":"Job Title\nRF Analog Layout Engineer - FinFET Technology\nSummary\nWe are looking for an RF-focused Analog Layout Engineer with expertise in FinFET nodes. The candidate will design layouts for high-frequency analog/RF blocks, ensuring optimal performance under stringent parasitic and matching constraints.\nKey Responsibilities\nLayout design for RF circuits such as LNAs, mixers, VCOs, and PLL sub-blocks in FinFET technology.\nOptimize routing for high-frequency signals, minimizing parasitic capacitance and inductance.\nImplement shielding strategies (coaxial, differential, ground shields) to reduce coupling and crosstalk.\nAddress EM/IR reliability for high-current RF paths and ensure compliance with advanced DRC/LVS rules.\nApply matching techniques for RF differential pairs and passive components (inductors, capacitors).\nCollaborate with RF designers to meet performance targets for gain, noise figure, and phase noise.\nEnsure compliance with color-aware routing and multi-patterning constraints for RF metal layers.\nRequired Skills\nHands-on experience in RF layout design at FinFET nodes.\nDeep understanding of parasitic control for high-frequency circuits.\nFamiliarity with EM modeling, substrate coupling, and isolation techniques.\nProficiency in RF-aware EDA tools and post-layout simulation flows.\nKnowledge of reliability \nPreferred Skills\nExperience with RF sign-off flows and EM extraction tools.\nAbility to optimize layout for low phase noise and high linearity.\nScripting skills for RF layout automation and verification.","description_format":"text","description_chars":1536,"description_truncated":false,"requirements":{"experience_years_min":null,"management_years_min":null,"team_size_min":null,"manages_managers":false,"education":null,"security_clearance":false,"languages":[]},"benefits":[],"hiring_locations":[],"hiring_excludes":[],"relocation_offered":false,"industries":["Cybersecurity","Government","Science & Engineering","Research Institutes"],"lifecycle":[{"event":"open","at":"2026-10-03T19:10:09Z"}],"visa":[],"liveness":{"score":22,"band":"cold","label":"Long shot","p_open":1,"p_active":0.402,"p_room":0.55,"age_days":28,"expected_fill_days":27,"reasons":["conf:1","stale_co","velocity","win:tail","comp:brand"],"computed_at":"2026-10-10T05:45:15Z"},"pay":null,"html_url":"https://alion.io/job/capgemini-rf-analog-layout-engineer-2","json_url":"https://alion.io/job/capgemini-rf-analog-layout-engineer-2.json","meta":{"generated_at":"2026-10-11T04:56:35Z","cache_seconds":300,"methodology":"https://alion.io/methodology","terms":"https://alion.io/terms","contact":"https://alion.io/contact","api":"https://alion.io/developers","about":"Alion is a live layer of people, companies and AI agents: who they are, whether they are real and active right now, what they do and how to work with them, readable by people and by agents and paid per call.","catalog":"https://alion.io/catalog.json","usage":{"tier":"crawler","counted_by":"address","units_charged":1,"used_today":4147,"day_limit":5000,"remaining_today":853,"minute_limit":60,"resets_at":"2026-10-12T00:00:00Z"}},"offers":[{"id":"company.slices","title":"One company in depth, by slice","status":"live","price":{"credits":0.02,"usd":0.002,"plus_per_slice":{"credits":0.05,"usd":0.005}},"unit":"per company, plus each slice with data","note":"the employer in depth","call":{"mcp_tool":"get_company","arguments":{"id":145},"rest":"https://alion.io/mcp/rest/get_company?id=145"},"human":"https://alion.io/catalog?offer=company.slices&for=job%2Fcapgemini-rf-analog-layout-engineer-2"},{"id":"market.stats","title":"A market slice: pay, demand and time to fill","status":"live","price":{"credits":1,"usd":0.1},"unit":"per slice","note":"pay, demand and time to fill for this role and place","call":{"mcp_tool":"market_stats"},"human":"https://alion.io/catalog?offer=market.stats&for=job%2Fcapgemini-rf-analog-layout-engineer-2"},{"id":"job.search","title":"Open jobs by role, technology, place, pay and visa","status":"live","price":{"credits":0.02,"usd":0.002},"unit":"per posting in a list","note":"similar open postings","call":{"mcp_tool":"search_jobs"},"human":"https://alion.io/catalog?offer=job.search&for=job%2Fcapgemini-rf-analog-layout-engineer-2"},{"id":"company.verify","title":"Is this company real and active right now","status":"pilot","price":null,"unit":"per company","request":{"url":"https://alion.io/catalog/request","method":"POST","body":"{\"offer\": \"company.verify\", \"for\": \"job/capgemini-rf-analog-layout-engineer-2\", \"note\": \"what you need it for\"}"},"human":"https://alion.io/catalog?offer=company.verify&for=job%2Fcapgemini-rf-analog-layout-engineer-2"}]}