{"id":3185043,"url":"https://alion.io/job/capgemini-senior-engineer-semicon-dv-rtl-pd-dft","title":"Senior Engineer Semicon - DV, RTL, PD, DFT","company":{"id":145,"name":"Capgemini","domain":"capgemini.com","url":"https://alion.io/company/capgemini","size_band":"5000+","is_staffing_agency":false,"employer_type":"services","is_intermediary":false,"listed_via":null,"ats_vendor":"Career site","truth_index":{"grade":"B","score":80,"open_postings":1815,"ghost_share":0.002,"stale_share":0.807,"repost_share":0.013,"time_to_fill_p50_days":29,"computed_at":"2026-11-01T06:10:25Z"}},"role":"Hardware","role_family":"Hardware","seniority":"senior","employment_type":"full_time","work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":[],"countries":[],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":{"min_usd":28000,"max_usd":65000,"period":"year","method":"global_role_cell_scaled_by_country","sample_n":1936},"experience_years_min":8,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"Formal Verification","optional":false},{"name":"Perl","optional":false},{"name":"Python","optional":false},{"name":"SystemVerilog","optional":false},{"name":"UVM","optional":false},{"name":"Verilog","optional":false},{"name":"VHDL","optional":false},{"name":"Tessent","optional":true}],"status":"live","first_seen_at":"2026-10-23T14:41:53Z","employer_posted_date":"2026-10-23","last_verified_at":"2026-11-01T06:37:38Z","board_verified":true,"closed_at":null,"days_open":8,"trust":{"level":"ok","repost_count":null,"flags":[],"days_open":8},"description":"About Capgemini:\nAt Capgemini Engineering, the world leader in engineering services, we bring together a global team of engineers, scientists, and architects to help the world’s most innovative companies unleash their potential. From autonomous cars to life-saving robots, our digital and software technology experts think outside the box as they provide unique R&D and engineering services across all industries. Join us for a career full of opportunities. Where you can make a difference. Where no two days are the same.\nYour role:\nDV role:\nOwn verification of IP’s and SoC’s in prototype and SoC design environment\nEstablish functional and performance benchmarks\nLead the definition, execution, and continuous improvement of a robust design verification (DV) methodology and tools flow across different verification platforms\nIP and SoC design verification (DV), from the RTL level to emulation, resulting in fully functional and performant IP’s/SoC’s.\nYour profile:\nSound basics of system Verilog, and good experience in constrained Random and Coverage Driven Verification with UVM/OVM\nExperience in creating any UVC components or sequences is must\nBasic knowledge on at least two of these: AHB/AXI, PCIe/CXL, USB, DDR, Serial protocols, Processor Verification etc. Expertise in one protocol is a must for Senior and above.\nShould be comfortable in updating the existing verification environment for feature updates. (bring-up/Architect UVM based Test bench from Scratch is a strong plus)\nEDA simulation/debugging tools agnostic\nGood knowledge of Perl/TCL/Python scripting\nDomain expertise on any one of these for senior and above: CPU processor/server, multimedia, automotive, Ethernet, Mobile.\nRTL role:\nOwn feasibility studies for defining the system architecture, requirements, and external interfaces\nDevelop microarchitecture and logic design in collaboration with functional leads to deliver design from architecture to tape-out\nPerform RTL coding, Lint checks, CDC tests, and creating timing constraint files\nWork closely with Synthesis, STA, PD, and DFT teams to meet all functional requirements, performance, power, and area goals\nDevelop flows and tools as necessary in support of design activities.\nYour profile:\n8+ year experience in VLSI design\nBSC/MSC in Electrical/Computer engineering\nStrong Verilog/System Verilog or VHDL skills\nExperience in defining microarchitecture and design of complex design units\nSoC design experience\nProficient in advanced design practices (Lint, CDC, and Low Power Design)\nProficient with the various backend tools (synthesis and STA)\nFamiliar with CPU (ARM, RISC-V, or x86) instruction set\nProficiency using Perl/C/Python scripting and programming\n Verification methodologies understanding\nGood communication and interpersonal skills.\nPD role:\n Responsible for all aspects of Physical Design in full chip or block level in extremely advanced technologies nodes (10nm and below)\nIn deep Floorplanning, partitioning/budgeting, power mesh distribution, clock tree planning and analysis, Scan re-ordering, placement, CTS, place and route\nCover all relevant activities related to timing analysis (closure through sign-off including SI/noise) ECO tasks (both functional and timing)\nIn charge with all validation/qualification tasks : Formal Verification, EM/IR, DRC, LVS, Antenna, ERC analysis and fixes\nBe part of the overall Low Power solution development and implementation\nDevelop/enhance timing related scripts for clock skew analysis, critical path analysis, various IO interfaces, constraints partitioning/budgeting (from top-level to block level)\nComplete multiple design cycles of high complexity with little supervision.\nYour profile:\n8+ years (desirable) in challenging RTL2GDSII work done on 10nm or below nodes with 500k -1million+ instances in designs\nPower user of PnR and timing analysis CAD tools from Synopsys and/or Cadence\nGood knowledge of synthesis flow, insertDFT scan/coverage and optimization\nExcellent floorplan, power plan, CTS, place, route, and timing closure skills\nProficiency using Perl/TCL/Python scripting and Makefile\nExpertise in timing STA/PTSI - signal integrity closure, ECO generation/implementation skill\nExcellent EM/IR, DRC, LVS, ERC analysis and fixing skills\nExperience with sign-off tape-out closure work\nAny top level - floor planning, pin assignment - tape out activities is a plus.\nDFT role:\nDfT implementation inline with existing test methodology for advance process nodes\nPerform top and/or block-level DFT insertion: scan compression, (i)JTAG, ATPG, patterns validation/simulation, MBIST/LBIST\nClosely work with physical design team to resolve timing constraints/issues\nVerify DFT circuitry and interface with other components/IPs and debug timing simulation issues\nDebug and improve important DfT KPIs: test coverage/pattern efficiency\nHierarchical retargeting\nSilicon bring-up, diagnosis and support for physical failure analysis.\nYour profile:\n 6+ years of hands-on experience with DFT and test flows with commercial EDA tools for large and complex SOCs\nStrong fundamental knowledge of DFT techniques including JTAG, ATPG, yield learning, logic diagnosis, Scan compression, IEEE 1500 Std. and MBIST/LBIST\nExperience with one of the main EDAs providers: Synopsys DFT Complier, Tetramax, VCS, Tessent and Modus/Encounter tool suite\nExperience in RTL simulation, synthesis, Linting, CDC and RDC checks, STA, DFT, quality metrics is a plus\nHands-on in Perl/Tcl/Python scripting\n Excellent analytical, and problem-solving skills.\nWhat Will You Love About Working Here:\nCollaborative and Inclusive Culture: You’ll work alongside passionate engineers striving to provide the best service to our clients and communities with shared interests and identities, in a dynamic environment involving teams spread across different global locations.\nFlexibility and Growth: Enjoy flexible working hours and access to a wide range of professional development opportunities, including training programs, learning platforms and certifications. Whether you're diving into Generative AI, data science, or sustainability, our digital campus supports your learning journey every step of the way;\n Comprehensive Benefits: Benefit from an attractive package including medical services, eye glasses coverage, Benefit online, meal tickets, Employee Assistance Program (covering financial, legal, and emotional matters), and the Employee Share Option Plan.\nCapgemini Romania is an equal opportunity employer. We promote equality and dignity in all aspects of recruitment and employment, and all offers of employment and promotions are made on the basis of performance, competence and ability.\nAbout CAPGEMINI:\nCapgemini is the business transformation partner for enterprises in the age of AI. We help organizations imagine and build an intelligent, sustainable future, combining AI, technology and human ingenuity to transform how they operate, innovate and grow. With unique end-to-end capabilities spanning strategy, technology, engineering and intelligent operations, we bring together deep industry expertise and market-leading capabilities in AI, cloud and data to turn ambition into measurable business outcomes at scale. Supported by a robust ecosystem of partners and nearly 60 years of expertise, Capgemini is a responsible and diverse global organization of over 410,000 team members in more than 50 countries","description_format":"text","description_chars":7391,"description_truncated":false,"requirements":{"experience_years_min":8,"management_years_min":null,"team_size_min":null,"manages_managers":false,"education":{"level":"bachelor","optional":false},"security_clearance":false,"languages":[]},"benefits":["Flexible schedule","Professional development"],"hiring_locations":[],"hiring_excludes":[],"relocation_offered":false,"industries":["IT Consulting & Digital Transformation","Systems Integrators","Management Consulting","Engineering Services"],"lifecycle":[{"event":"open","at":"2026-10-23T23:09:09Z"}],"visa":[{"country":"US","licensed_sponsor":true,"evidence":"H-1B filings in 12 months: 2,076 · green card filings: 82","filings_12m":2076,"filings_prev_12m":2803,"green_card_filings_12m":82,"median_offered_wage_usd":132120,"route":null,"cap_exempt":false,"checked_at":"2026-10-29T16:27:21+00:00","sources":["US Department of Labor: LCA disclosure data (H-1B, H-1B1, E-3)","US Department of Labor: PERM disclosure data (green cards)"],"filings_for_role_12m":15},{"country":"CA","licensed_sponsor":true,"evidence":"Positions approved through LMIA in 12 months: 11","filings_12m":11,"filings_prev_12m":10,"green_card_filings_12m":null,"median_offered_wage_usd":null,"route":"Global Talent Stream; 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