{"id":1899444,"url":"https://alion.io/job/capgemini-senior-rtl-design-engineer","title":"Senior RTL Design Engineer","company":{"id":145,"name":"Capgemini","domain":"capgemini.com","url":"https://alion.io/company/capgemini","size_band":"5000+","is_staffing_agency":false,"employer_type":"services","is_intermediary":false,"listed_via":null,"ats_vendor":"Career site","truth_index":{"grade":"B","score":75,"open_postings":915,"ghost_share":0,"stale_share":1,"repost_share":0,"time_to_fill_p50_days":23,"computed_at":"2026-10-05T05:45:15Z"}},"role":"Hardware","role_family":"Hardware","seniority":"senior","employment_type":"full_time","work_mode":"remote","remote_scope":"stated_countries","remote_scope_basis":"board_field","remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Odesa, Ukraine"],"countries":["UA"],"hiring_countries":["UA"],"hiring_countries_total":1,"salary":null,"salary_estimate":{"min_usd":35000,"max_usd":81000,"period":"year","method":"global_role_cell_scaled_by_country","sample_n":1439},"experience_years_min":8,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"Perl","optional":false},{"name":"Python","optional":false},{"name":"SystemVerilog","optional":false},{"name":"Verilog","optional":false},{"name":"VHDL","optional":false}],"status":"live","first_seen_at":"2026-10-05T09:53:55Z","employer_posted_date":"2026-10-05","last_verified_at":"2026-10-06T02:05:51Z","board_verified":true,"closed_at":null,"days_open":0,"trust":{"level":"ok","repost_count":null,"flags":[],"days_open":0},"description":"At Capgemini Engineering, the world leader in engineering services, we bring together a global team of engineers, scientists, and architects to help the world’s most innovative companies unleash their potential. From autonomous cars to life-saving robots, our digital and software technology experts think outside the box as they provide unique R&D and engineering services across all industries. Join us for a career full of opportunities. Where you can make a difference. Where no two days are the same.\nJob Description\n8+ years of experience in VLSI design.\nBSc/MSc in Electrical or Computer Engineering\nStrong Verilog/SystemVerilog or VHDL skills\nExperience defining microarchitecture and designing complex digital blocks and subsystems\nStrong SoC design experience\nProficiency in advanced design methodologies including Lint, CDC, RDC, and Low Power Design\nExperience with backend flows, including synthesis and static timing analysis (STA).\nFamiliarity with CPU architectures and instruction sets (ARM, RISC-V, or x86).\nExperience with scripting and programming languages such as Python, Perl, or C.\nUnderstanding of modern verification methodologies and design sign-off flows.\nExperience with Synopsys VC Static CDC/RDC or equivalent verification tools is an advantage.\nStrong analytical, debugging, communication, and collaboration skills.\nOwn feasibility studies for defining system architecture, requirements, and external interfaces.\nDevelop microarchitecture and RTL design in collaboration with architecture and functional teams, driving projects from specification through tape-out.\nPerform RTL coding, linting, CDC/RDC analysis, and development of timing constraint files (SDC).\nExecute and manage CDC/RDC verification activities at IP, subsystem, and SoC levels to ensure successful design sign-off.\nReview RTL implementations, investigate tool-reported violations, identify root causes, and distinguish genuine design issues from false positives through proper waiver definition.\nDefine and maintain CDC/RDC constraints (SDC/SGDC), verification environments, and SoC operating modes.\nDevelop, automate, and improve CDC/RDC verification flows based on Synopsys VC Static CDC/RDC tools.\nDefine and implement methodologies for automatic generation of IP abstraction models.\nRun and analyze multiple CDC/RDC verification scenarios across different use cases and operating modes.\nCollaborate closely with RTL designers and IP owners to propose robust architectural and RTL solutions for CDC/RDC issues.\nVerify implementation fixes and ensure closure of all CDC/RDC sign-off criteria.\nWork closely with Synthesis, STA, Physical Design, DFT, and Verification teams to achieve functional, timing, power, and area targets.\nDevelop design methodologies, automation scripts, and engineering tools to improve productivity and design quality.\nWhat you will love working here\nWe care about all our employees and want them to feel as comfortable as possible. That's why we offer health insurance from the first days, regardless of the probationary period.\nThe Gift from the Company - Christmas holidays from December 25 to December 31.\nCooperation with Superhumans center and Veteran HUB. Capgemini Engineering has supported the launch of psychological rehabilitation department of Superhumans. Our team also donated over UAH 500 000 prosthetics for three Ukrainian defenders. Currently, we support psychological counseling provided by the Veteran Hub, and we have implemented an internal policy making the company friendly to military and veterans with the assistance of the Hub.\nCapgemini is a global business and technology transformation partner, helping organizations to accelerate their dual transition to a digital and sustainable world, while creating tangible impact for enterprises and society. It is a responsible and diverse group of 340,000 team members in more than 50 countries. With its strong over 55-year heritage, Capgemini is trusted by its clients to unlock the value of technology to address the entire breadth of their business needs. It delivers end-to-end services and solutions leveraging strengths from strategy and design to engineering, all fueled by its market leading capabilities in AI, generative AI, cloud and data, combined with its deep industry expertise and partner ecosystem.\n#LI-ID3\n#LI-Remote","description_format":"text","description_chars":4335,"description_truncated":false,"requirements":{"experience_years_min":8,"management_years_min":null,"team_size_min":null,"manages_managers":false,"education":{"level":"bachelor","optional":false},"security_clearance":false,"languages":[]},"benefits":["Health insurance"],"hiring_locations":[{"name":"Ukraine","iso":"UA","kind":"country"}],"hiring_excludes":[],"relocation_offered":false,"industries":["Cybersecurity","Government","Science & Engineering","Research Institutes"],"lifecycle":[{"event":"open","at":"2026-10-05T09:58:49Z"}],"visa":[],"liveness":{"score":86,"band":"hot","label":"Hiring now","p_open":1,"p_active":0.86,"p_room":1,"age_days":0,"expected_fill_days":23,"reasons":["conf:0","win:early","comp:brand"],"computed_at":"2026-10-06T02:59:24Z"},"pay":null,"html_url":"https://alion.io/job/capgemini-senior-rtl-design-engineer","json_url":"https://alion.io/job/capgemini-senior-rtl-design-engineer.json","meta":{"generated_at":"2026-10-06T02:59:24Z","cache_seconds":300,"methodology":"https://alion.io/methodology","terms":"https://alion.io/terms","contact":"https://alion.io/contact","api":"https://alion.io/developers","about":"Alion is a live layer of people, companies and AI agents: who they are, whether they are real and active right now, what they do and how to work with them, readable by people and by agents and paid per call.","catalog":"https://alion.io/catalog.json","usage":{"tier":"crawler","counted_by":"address","units_charged":1,"used_today":4505,"day_limit":5000,"remaining_today":495,"minute_limit":60,"resets_at":"2026-10-07T00:00:00Z"}},"offers":[{"id":"company.slices","title":"One company in depth, by slice","status":"live","price":{"credits":0.02,"usd":0.002,"plus_per_slice":{"credits":0.05,"usd":0.005}},"unit":"per company, plus each slice with data","note":"the employer in depth","call":{"mcp_tool":"get_company","arguments":{"id":145},"rest":"https://alion.io/mcp/rest/get_company?id=145"},"human":"https://alion.io/catalog?offer=company.slices&for=job%2Fcapgemini-senior-rtl-design-engineer"},{"id":"market.stats","title":"A market slice: pay, demand and time to fill","status":"live","price":{"credits":1,"usd":0.1},"unit":"per slice","note":"pay, demand and time to fill for this role and place","call":{"mcp_tool":"market_stats"},"human":"https://alion.io/catalog?offer=market.stats&for=job%2Fcapgemini-senior-rtl-design-engineer"},{"id":"job.search","title":"Open jobs by role, technology, place, pay and visa","status":"live","price":{"credits":0.02,"usd":0.002},"unit":"per posting in a list","note":"similar open postings","call":{"mcp_tool":"search_jobs"},"human":"https://alion.io/catalog?offer=job.search&for=job%2Fcapgemini-senior-rtl-design-engineer"},{"id":"company.verify","title":"Is this company real and active right now","status":"pilot","price":null,"unit":"per company","request":{"url":"https://alion.io/catalog/request","method":"POST","body":"{\"offer\": \"company.verify\", \"for\": \"job/capgemini-senior-rtl-design-engineer\", \"note\": \"what you need it for\"}"},"human":"https://alion.io/catalog?offer=company.verify&for=job%2Fcapgemini-senior-rtl-design-engineer"}]}