{"id":1805706,"url":"https://alion.io/job/capgemini-vlsi-dft-architect","title":"VLSI - DFT Architect","company":{"id":145,"name":"Capgemini","domain":"capgemini.com","url":"https://alion.io/company/capgemini","size_band":"5000+","is_staffing_agency":false,"employer_type":"services","is_intermediary":false,"listed_via":null,"ats_vendor":"Career site","truth_index":{"grade":"B","score":75,"open_postings":932,"ghost_share":0,"stale_share":0.996,"repost_share":0,"time_to_fill_p50_days":26,"computed_at":"2026-10-06T05:45:30Z"}},"role":"Hardware","role_family":"Hardware","seniority":"staff","employment_type":"full_time","work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Bengaluru, India"],"countries":["IN"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":{"min_usd":26000,"max_usd":53000,"period":"year","method":"global_role_cell_scaled_by_country","sample_n":459},"experience_years_min":15,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"HPC","optional":false},{"name":"Perl","optional":false},{"name":"Python","optional":false},{"name":"Synopsys DFTMAX","optional":false},{"name":"Synopsys Fusion Compiler","optional":false},{"name":"Synopsys TestMAX","optional":false},{"name":"Tessent","optional":false}],"status":"closed","first_seen_at":"2026-09-02T08:36:09Z","employer_posted_date":"2026-09-28","last_verified_at":"2026-10-06T07:01:33Z","board_verified":false,"closed_at":"2026-10-06T07:01:33Z","days_open":33,"trust":{"level":"not_scored","repost_count":null,"flags":[],"days_open":33},"description":"Your Role\nLead DFT execution across IP and SoC programs from architecture to silicon production.\nDefine and implement Scan, Scan Compression (EDT), ATPG, MBIST, JTAG (IEEE 1149.1), IEEE 1500, and IEEE 1687 (iJTAG) solutions.\nDrive scan insertion, DFT integration, and sign-off using industry-standard EDA tools.\nGenerate and optimize ATPG patterns to achieve high fault coverage and production test goals.\nPerform DFT DRC checks, coverage analysis, and debug scan, compression, and ATPG issues.\nDevelop and validate STA constraints for various test modes.\nSupport silicon bring-up, failure diagnosis, yield improvement, and production ramp activities.\nCollaborate with RTL, Verification, Physical Design, Product Engineering, and Manufacturing teams to resolve test-related challenges.\nDevelop automation solutions using TCL, Perl, Python, and Shell scripting to improve productivity and quality.\nMentor junior engineers, drive technical excellence, and contribute to DFT methodology improvements across programs.\nYour Profile\n15 to 20+ years of hands-on experience in Design-for-Test (DFT) for ASIC and SoC development.\nProven experience leading end-to-end DFT implementation for multiple successful SoC tape-outs.\nStrong expertise in Scan Insertion, Scan Compression (EDT), ATPG, MBIST, LBIST, JTAG (IEEE 1149.1), IEEE 1500, and IEEE 1687 (iJTAG).\nHands-on experience with Synopsys TestMAX/DFTMAX, TetraMAX, Fusion Compiler, Siemens Tessent Suite, or Cadence Modus tools.\nDeep understanding of fault models including Stuck-at, Transition, Path Delay, Bridge Fault, and Cell-Aware ATPG methodologies.\nExperience in DFT verification, DRC closure, ATPG pattern validation, and fault coverage optimization.\nStrong knowledge of timing constraints, STA for test modes, clocking architectures, and low-power DFT methodologies.\nExperience supporting silicon bring-up, tester debug, diagnosis, yield improvement, and production ramp activities.\nProficiency in TCL, Perl, Python, and Shell scripting for automation and methodology development.\nWhat Will You Love Working at Capgemini?\nWork with some of the world’s leading semiconductor and technology companies on cutting-edge ASIC, SoC, AI, Automotive, Networking, and HPC programs.\nGain exposure to the complete silicon lifecycle, from architecture, design, verification, DFT, physical implementation, tape-out, silicon bring-up, and production support.\nCollaborate with globally distributed engineering teams across North America, Europe, and Asia.Access continuous learning opportunities through Capgemini’s training, certification, and technical upskilling programs.","description_format":"text","description_chars":2614,"description_truncated":false,"requirements":{"experience_years_min":15,"management_years_min":null,"team_size_min":null,"manages_managers":false,"education":null,"security_clearance":false,"languages":[]},"benefits":["Continuous learning"],"hiring_locations":[],"hiring_excludes":[],"relocation_offered":false,"industries":["Cybersecurity","Government","Science & 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