{"id":1989215,"url":"https://alion.io/job/career-makers-architectlead-2","title":"Architect/Lead","company":{"id":3800593,"name":"Career Makers","domain":"career-makers.com","url":"https://alion.io/company/career-makers","size_band":null,"is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":null,"truth_index":null},"role":"Hardware","role_family":"Hardware","seniority":"lead","employment_type":null,"work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Bengaluru, India"],"countries":["IN"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":{"min_usd":28000,"max_usd":64000,"period":"year","method":"global_role_cell_scaled_by_country","sample_n":677},"experience_years_min":5,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"SystemVerilog","optional":false},{"name":"UVM","optional":false}],"status":"live","first_seen_at":"2026-10-07T02:44:18Z","employer_posted_date":null,"last_verified_at":"2026-10-07T02:44:18Z","board_verified":false,"closed_at":null,"days_open":7,"trust":{"level":"not_scored","repost_count":null,"flags":[],"days_open":7},"description":"About the Role :\n\nThe role involves building and maintaining scalable testbenches, performing functional verification of complex SoCs and subsystems, and collaborating with cross-functional teams to ensure high-quality silicon. The ideal candidate will have experience with AMBA protocols and power management features verification.\n\nKey Responsibilities :\n\n- Develop and execute verification plans for SoC/IP level designs\n\n- Build and maintain scalable testbenches using SystemVerilog/UVM methodology\n\n- Perform functional verification of complex SoCs and subsystems\n\n- Work on AMBA protocols (AXI/AHB/APB) verification\n\n- Verify power management features (PMU, low-power scenarios, UPF-based verification)\n\n- Debug simulation failures and root-cause issues efficiently\n\n- Collaborate with design, architecture, and validation teams to ensure high-quality silicon\n\n- Contribute to coverage closure (functional & code coverage)\n\nRequired Skills :\n\n- Strong background in functional verification\n\n- Experience with SystemVerilog/UVM methodology\n\n- Knowledge of AMBA protocols (AXI/AHB/APB)\n\n- Understanding of power management features (PMU, low-power scenarios, UPF-based verification)\n\nPreferred Skills :\n\n- Experience with coverage-driven verification\n\n- Knowledge of simulation tools and methodologies\n\n- Strong debugging and problem-solving skills\n\nQualifications :\n\n- Strong technical skills and attention to detail\n\n- Ability to work in a team environment and collaborate with cross-functional teams\n\n- Good communication and interpersonal skills\n\nBenefits :\n\n- Opportunity to work on complex SoC/IP level designs\n\n- Collaborative team environment\n\n- Professional development opportunities\n\nInterview Process :\n\n- Initial screening of resumes and cover letters\n\n- Technical interview with the verification team\n\n- Final interview with the hiring manager\n\nRecruiter Summary in 5 concise bullets :\n\n- Develop and execute verification plans for SoC/IP level designs\n\n- Build and maintain scalable testbenches using SystemVerilog/UVM methodology\n\n- Perform functional verification of complex SoCs and subsystems\n\n- Collaborate with cross-functional teams to ensure high-quality silicon\n\n- Contribute to coverage closure and debug simulation failures efficiently\nSkills\nDesign Verification, SoC, System Verilog, UVM, AMBA, IP Design, Simulink, Verification, IP Verification","description_format":"text","description_chars":2375,"description_truncated":false,"requirements":{"experience_years_min":5,"management_years_min":null,"team_size_min":null,"manages_managers":false,"education":null,"security_clearance":false,"languages":[]},"benefits":["Professional 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