DFT Engineer - SoC
First seen by Alion on Oct 22, 2026.
Job Description :
We are seeking a highly skilled and experienced professional to join our team as a Design for Testability (DFT) Engineer. The successful candidate will be responsible for the development and implementation of DFT methodologies and techniques to ensure the testability of complex digital designs.
About the Role :
The role involves working on various aspects of DFT, including RTL DFT insertions and verification, SSN implementation and validation, and IJTAG insertion and verification. The candidate will also be responsible for MBIST insertion, memory repair configuration, and verification, as well as EDT-based scan compression insertion and validation.
Key Responsibilities :
- RTL DFT insertions and verification
- SSN implementation and validation
- IJTAG (IEEE 1687) insertion and verification - Block and SoC level
- MBIST insertion, memory repair configuration, and verification - Block and SoC level
- EDT-based scan compression insertion and validation
- Netlist insertions and Pattern verification
- Gate-level scan stitching and DRC checks
- LBIST architecture implementation and validation
- ATPG pattern generation (stuck-at/transition) and GLS simulations
- Coverage analysis, debug, and pattern optimization
- Post-silicon bring-up, ATE support, and silicon debug
Required Skills :
- Strong knowledge of DFT methodologies and techniques
- Experience with IJTAG, MBIST, and EDT-based scan compression
- Proficiency in ATPG pattern generation and GLS simulations
- Strong understanding of digital design principles and testability concepts
- Excellent analytical and problem-solving skills
Preferred Skills :
- Experience with gate-level scan stitching and DRC checks
- Knowledge of LBIST architecture implementation and validation
- Familiarity with post-silicon bring-up, ATE support, and silicon debug
Qualifications :
- Bachelor's or Master's degree in Electrical Engineering, Computer Science, or related field
- Strong academic record and relevant work experience
Benefits :
- Opportunity to work on complex and challenging projects
- Collaborative and dynamic work environment
- Professional development and growth opportunities
Interview Process :
- Initial screening and shortlisting of candidates
- Technical interview with the engineering team
- Final interview with the hiring manager
Skills
DFT, RTL Design, SoC, Verification, System Verilog, LBIST, ATPG, MBIST, System Configuration