{"id":2985046,"url":"https://alion.io/job/castelion-senior-fpga-engineer","title":"Senior FPGA Engineer","company":{"id":1795053,"name":"Castelion","domain":"castelion.com","url":"https://alion.io/company/castelion","size_band":"1001-5000","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Greenhouse","truth_index":null},"role":"Hardware","role_family":"Hardware","seniority":"senior","employment_type":"full_time","work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Allen, United States"],"countries":["US"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":{"min_usd":103000,"max_usd":189000,"period":"year","method":"role_seniority_country_remote_cell","sample_n":1396},"experience_years_min":null,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"C++","optional":false},{"name":"Verilog","optional":false},{"name":"VHDL","optional":false},{"name":"Vitis","optional":false},{"name":"Vitis HLS","optional":false},{"name":"Xilinx Vivado","optional":true}],"status":"live","first_seen_at":"2026-09-25T01:26:59Z","employer_posted_date":"2026-09-25","last_verified_at":"2026-10-23T04:55:22Z","board_verified":true,"closed_at":null,"days_open":28,"trust":{"level":"ok","repost_count":null,"flags":[],"days_open":28},"description":"Why Castelion, Why Now \nCastelion is moving incredibly fast to develop and deliver advanced defense systems at a time when execution matters more than ever. We believe focus, ownership, and excellence are decisive advantages - and we're building a world-class team to turn bold ideas into real capability. \nThis is a rare opportunity to join at an early stage, where you'll have significant ownership, collaborate with exceptional teammates, and make a direct, measurable impact on our mission and the future of the company - regardless of your function. \nSenior FPGA Engineer\nCastelion is seeking a Senior FPGA Engineer with strong experience in Vitis HLS and High-Level Synthesis workflows to support the development of high-performance digital systems for mission-critical hardware. This is a high-impact, full-time role focused on accelerating FPGA development by translating algorithmic and system-level requirements into efficient FPGA implementations using C/C++-based design flows.\nYou will work closely with our hardware, software, and systems engineering teams to implement and optimize FPGA-based processing capabilities. This role is ideal for an engineer who can ramp quickly, contribute immediately, and deliver optimized hardware implementations in a fast-moving development environment.\nResponsibilities\nDevelop FPGA-based implementations using Vitis HLS to generate VHDL/Verilog from C/C++ code\nTranslate algorithms and system requirements into efficient hardware architectures optimized for performance and latency\nDevelop and optimize high-level synthesis pipelines and dataflow architectures\nCollaborate with software, avionics, and systems engineers to integrate FPGA functionality into embedded platforms\nPerform FPGA simulation, synthesis, timing analysis, and hardware validation\nOptimize designs for throughput, determinism, and resource utilization\nSupport hardware integration, board bring-up, and debugging as needed\nContribute to verification and testing of FPGA functionality\nBasic Qualifications\nBachelor's degree in Electrical Engineering, Computer Engineering, or related technical field\nDemonstrated experience using Vitis HLS or similar High-Level Synthesis tools\nStrong C/C++ programming experience for hardware-oriented development\nExperience generating VHDL or Verilog from HLS workflows\nFamiliarity with FPGA development flows including simulation, synthesis, and timing closure\nExperience with Xilinx/AMD FPGA platforms and toolchains\nPreferred Skills and Experience\nExperience with high-throughput signal processing, sensor processing, or real-time embedded systems\nExperience optimizing HLS pipelines for latency, parallelism, and memory bandwidth\nFamiliarity with AXI interfaces, DMA, and FPGA-based accelerators\nExperience with Vivado and Vitis development environments\nBackground in aerospace, defense, robotics, or other high-performance embedded systems\nCastelion offers a generous benefits package. Please refer to the bottom of our Careers page for more details. \nOther Duties \nPlease note this job description is not designed to cover or contain a comprehensive listing of activities, duties or responsibilities that are required of the employee for this job. Duties, responsibilities and activities may change at any time with or without notice. \nAdditional Eligibility Requirements \nThis position may require access to classified information or restricted U.S. Government sites, systems, or information, as determined by the Company and/or applicable U.S. Government requirements. If the position is so designated, your employment in the role may be contingent upon your ability to obtain and maintain the required U.S. Government security clearance or other government authorization, and to satisfy any citizenship or other eligibility requirements imposed by applicable law, regulation, executive order, or government contract requirements. You will be notified if and when such requirements apply. \nAffirmative Action/EEO Statement \nCastelion is an Equal Opportunity Employer. We are committed to providing equal employment opportunities to all applicants and employees without regard to race, color, religion, sex, sexual orientation, gender identity, national origin, age, disability, genetic information, protected veteran status, or any other characteristic protected by applicable federal, state, or local law. \nCastelion is committed to providing reasonable accommodations to qualified individuals with disabilities throughout the application and hiring process. If you require a reasonable accommodation to complete an application, participate in the interview process, or otherwise participate in the hiring process, please contact . Requests for accommodation will be considered on an individual basis and handled in accordance with applicable law. \nCastelion is committed to fostering a workplace where employment decisions are based on qualifications, business needs, and the ability to perform the essential functions of the role, with or without reasonable accommodation. \nEAR/ITAR Requirements \nThis position requires access to export-controlled information, and as such, employment (or hiring of a contractor) is contingent upon the candidate’s ability to access all applicable export-controlled information without additional export licensing being required by the Bureau of Industry and Security and/or the Directorate of Defense Trade Controls.","description_format":"text","description_chars":5433,"description_truncated":false,"requirements":{"experience_years_min":null,"management_years_min":null,"team_size_min":null,"manages_managers":false,"education":{"level":"bachelor","optional":false},"security_clearance":true,"languages":[]},"benefits":[],"hiring_locations":[{"name":"United States","iso":"US","kind":"country"}],"hiring_excludes":[],"relocation_offered":false,"industries":["Missiles","Defense Manufacturing"],"lifecycle":[{"event":"open","at":"2026-10-21T08:14:48Z"}],"visa":[],"liveness":{"score":56,"band":"ok","label":"Likely open","p_open":1,"p_active":0.747,"p_room":0.75,"age_days":27,"expected_fill_days":29,"reasons":["conf:0","win:late","comp:brand"],"computed_at":"2026-10-22T06:10:10Z"},"pay":null,"html_url":"https://alion.io/job/castelion-senior-fpga-engineer","json_url":"https://alion.io/job/castelion-senior-fpga-engineer.json","meta":{"generated_at":"2026-10-23T05:55:02Z","cache_seconds":300,"methodology":"https://alion.io/methodology","terms":"https://alion.io/terms","contact":"https://alion.io/contact","api":"https://alion.io/developers","about":"Alion is a live layer of people, companies and AI agents: who they are, whether they are real and active right now, what they do and how to work with them, readable by people and by agents and paid per call.","catalog":"https://alion.io/catalog.json","usage":{"tier":"crawler_verified","counted_by":"address","units_charged":1,"used_today":9595,"day_limit":null,"remaining_today":null,"minute_limit":300,"resets_at":"2026-10-24T00:00:00Z"}},"offers":[{"id":"company.slices","title":"One company in depth, by slice","status":"live","price":{"credits":0.02,"usd":0.002,"plus_per_slice":{"credits":0.05,"usd":0.005}},"unit":"per company, plus each slice with data","note":"the employer in depth","call":{"mcp_tool":"get_company","arguments":{"id":1795053},"rest":"https://alion.io/mcp/rest/get_company?id=1795053"},"human":"https://alion.io/catalog?offer=company.slices&for=job%2Fcastelion-senior-fpga-engineer"},{"id":"market.stats","title":"A market slice: pay, demand and time to fill","status":"live","price":{"credits":1,"usd":0.1},"unit":"per slice","note":"pay, demand and time to fill for this role and place","call":{"mcp_tool":"market_stats"},"human":"https://alion.io/catalog?offer=market.stats&for=job%2Fcastelion-senior-fpga-engineer"},{"id":"job.search","title":"Open jobs by role, technology, place, pay and visa","status":"live","price":{"credits":0.02,"usd":0.002},"unit":"per posting in a list","note":"similar open postings","call":{"mcp_tool":"search_jobs"},"human":"https://alion.io/catalog?offer=job.search&for=job%2Fcastelion-senior-fpga-engineer"},{"id":"company.verify","title":"Is this company real and active right now","status":"pilot","price":null,"unit":"per company","request":{"url":"https://alion.io/catalog/request","method":"POST","body":"{\"offer\": \"company.verify\", \"for\": \"job/castelion-senior-fpga-engineer\", \"note\": \"what you need it for\"}"},"human":"https://alion.io/catalog?offer=company.verify&for=job%2Fcastelion-senior-fpga-engineer"}]}