{"id":3036459,"url":"https://alion.io/job/celero-communications-senior-asic-design-engineer-dspanalogserdes","title":"Senior ASIC Design Engineer - DSP/Analog/SerDes","company":{"id":668982,"name":"Celero Communications","domain":"celerocommunications.com","url":"https://alion.io/company/celerocommunications","size_band":"201-500","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Greenhouse","truth_index":{"grade":"B","score":80,"open_postings":5,"ghost_share":0,"stale_share":0.8,"repost_share":0,"time_to_fill_p50_days":35,"computed_at":"2026-10-26T05:57:25Z"}},"role":"Hardware","role_family":"Hardware","seniority":"senior","employment_type":null,"work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Ottawa, Canada"],"countries":["CA"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":{"min_usd":89000,"max_usd":156000,"period":"year","method":"role_seniority_country_remote_cell","sample_n":74},"experience_years_min":10,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"Formal Verification","optional":false},{"name":"Python","optional":false},{"name":"SystemVerilog","optional":false},{"name":"UVM","optional":false},{"name":"Verilog","optional":false},{"name":"MATLAB","optional":true}],"status":"live","first_seen_at":"2026-10-21T20:36:31Z","employer_posted_date":"2026-10-21","last_verified_at":"2026-10-26T22:39:17Z","board_verified":true,"closed_at":null,"days_open":5,"trust":{"level":"ok","repost_count":null,"flags":[],"days_open":5},"description":"Senior ASIC Design Engineer\nCelero Communications is an exciting and fast-growing semiconductor startup developing innovative technologies that power next-generation AI and data center infrastructure. Our products enable high-performance optical connectivity and next-generation optical transceivers and modems. Celero is seeking a highly skilled and motivated ASIC Design Engineer to join our team and contribute to the development of advanced ASICs for high-speed optical communication systems. The ideal candidate will have strong digital ASIC design expertise combined with hands-on experience in DSP, Analog, and/or SerDes technologies.\nDuties & Responsibilities:\nDesign and implement high-performance digital circuits and ASIC blocks using Verilog and SystemVerilog.\nDevelop and integrate DSP, digital communication, and high-speed SerDes functionality into complex ASIC designs.\nWork closely with Analog, SerDes, DSP, Architecture, Verification, Physical Design, and Systems teams to develop and integrate mixed-signal ASICs.\nParticipate in the design and development of high-speed data paths, signal processing blocks, control logic, and interfaces for optical communication systems.\nPerform synthesis, timing analysis, lint, formal equivalence, Clock Domain Crossing (CDC), and related ASIC implementation and signoff activities.\nOptimize designs for performance, power, and area (PPA).\nPerform RTL simulation and debugging to ensure design functionality and performance.\nContribute to block-level and top-level integration, verification, and silicon bring-up.\nParticipate in architecture and design reviews and provide technical guidance to other engineers.\nCollaborate with cross-functional teams to troubleshoot complex design and system-level issues.\nDevelop scripts and automation using Python, Tcl, or similar languages to improve design and verification efficiency.\nContribute to ASIC development from architecture and RTL through tapeout and silicon validation.\nRequired Qualifications:\nMaster’s or Ph.D. in Electrical Engineering, Computer Engineering, or a related technical field.\n10+ years of experience in digital ASIC design, with demonstrated ownership of complex ASIC blocks or subsystems.\nStrong proficiency in Verilog and/or SystemVerilog.\nStrong understanding of digital design principles, RTL design, and ASIC development methodologies.\nHands-on experience with ASIC design flows and industry-standard EDA tools.\n\nStrong knowledge of one or more of the following areas: \n- Digital Signal Processing (DSP)\n- High-speed SerDes\n- Analog/Mixed-Signal ICs\n- Digital communications\n- Optical communications\nExperience working with DSP algorithms, data-path architectures, FEC, equalization, modulation/demodulation, or other high-speed communication technologies.\nUnderstanding of SerDes architectures and high-speed interfaces, including TX/RX datapaths, equalization, clocking, and related mixed-signal interfaces.\nExperience collaborating with Analog and Mixed-Signal design teams and understanding the interaction between digital, analog, and SerDes blocks.\nExperience with synthesis, static timing analysis, Lint, CDC, formal verification, and RTL simulation.\nFamiliarity with verification methodologies such as UVM and/or formal verification.\nKnowledge of low-power design techniques and PPA optimization.\nStrong analytical and problem-solving skills.\nExcellent communication and teamwork skills with the ability to work effectively in a fast-paced startup environment.\nPreferred Qualifications\nExperience designing ASICs for optical communications, optical transceivers, coherent communications, or high-speed networking.\nExperience with coherent DSP, FEC, modulation schemes, equalization, or high-speed data recovery.\nExperience with SerDes architectures, including TX/RX, CDR, PLLs, CTLE, DFE, ADC/DAC interfaces, or related high-speed mixed-signal circuitry.\nExperience working with advanced semiconductor process technologies.\nExperience taking ASICs from architecture/RTL through synthesis, physical implementation, tapeout, and silicon bring-up.\nExperience with MATLAB, Python, Tcl, or other modeling and automation tools.\nUnderstanding of optical communication standards and high-speed networking protocols.\nExperience working in a startup or fast-paced semiconductor development environment.\nWhy Join Celero?\nAt Celero, you will have the opportunity to work on challenging, high-performance semiconductor technologies at the intersection of AI infrastructure, optical communications, DSP, SerDes, and mixed-signal design. You will work closely with experienced engineers across multiple disciplines and have the opportunity to make significant contributions to products from architecture through silicon.","description_format":"text","description_chars":4743,"description_truncated":false,"requirements":{"experience_years_min":10,"management_years_min":null,"team_size_min":null,"manages_managers":false,"education":{"level":"master","optional":false},"security_clearance":false,"languages":[]},"benefits":[],"hiring_locations":[],"hiring_excludes":[],"relocation_offered":false,"industries":["Telecom Infrastructure","Semiconductor IP & Chip Design Services"],"lifecycle":[{"event":"open","at":"2026-10-21T21:31:06Z"}],"visa":[],"liveness":{"score":90,"band":"hot","label":"Hiring now","p_open":1,"p_active":0.903,"p_room":1,"age_days":4,"expected_fill_days":35,"reasons":["conf:2","velocity","win:early"],"computed_at":"2026-10-26T05:57:25Z"},"pay":null,"html_url":"https://alion.io/job/celero-communications-senior-asic-design-engineer-dspanalogserdes","json_url":"https://alion.io/job/celero-communications-senior-asic-design-engineer-dspanalogserdes.json","meta":{"generated_at":"2026-10-26T22:45:09Z","cache_seconds":300,"methodology":"https://alion.io/methodology","terms":"https://alion.io/terms","contact":"https://alion.io/contact","api":"https://alion.io/developers","about":"Alion is a live layer of people, companies and AI agents: who they are, whether they are real and active right now, what they do and how to work with them, readable by people and by agents and paid per call.","catalog":"https://alion.io/catalog.json","usage":{"tier":"crawler_verified","counted_by":"address","units_charged":1,"used_today":30830,"day_limit":null,"remaining_today":null,"minute_limit":300,"resets_at":"2026-10-27T00:00:00Z"}},"offers":[{"id":"company.slices","title":"One company in depth, by slice","status":"live","price":{"credits":0.02,"usd":0.002,"plus_per_slice":{"credits":0.05,"usd":0.005}},"unit":"per company, plus each slice with data","note":"the employer in depth","call":{"mcp_tool":"get_company","arguments":{"id":668982},"rest":"https://alion.io/mcp/rest/get_company?id=668982"},"human":"https://alion.io/catalog?offer=company.slices&for=job%2Fcelero-communications-senior-asic-design-engineer-dspanalogserdes"},{"id":"market.stats","title":"A market slice: pay, demand and time to fill","status":"live","price":{"credits":1,"usd":0.1},"unit":"per slice","note":"pay, demand and time to fill for this role and place","call":{"mcp_tool":"market_stats"},"human":"https://alion.io/catalog?offer=market.stats&for=job%2Fcelero-communications-senior-asic-design-engineer-dspanalogserdes"},{"id":"job.search","title":"Open jobs by role, technology, place, pay and visa","status":"live","price":{"credits":0.02,"usd":0.002},"unit":"per posting in a list","note":"similar open postings","call":{"mcp_tool":"search_jobs"},"human":"https://alion.io/catalog?offer=job.search&for=job%2Fcelero-communications-senior-asic-design-engineer-dspanalogserdes"},{"id":"company.verify","title":"Is this company real and active right now","status":"pilot","price":null,"unit":"per company","request":{"url":"https://alion.io/catalog/request","method":"POST","body":"{\"offer\": \"company.verify\", \"for\": \"job/celero-communications-senior-asic-design-engineer-dspanalogserdes\", \"note\": \"what you need it for\"}"},"human":"https://alion.io/catalog?offer=company.verify&for=job%2Fcelero-communications-senior-asic-design-engineer-dspanalogserdes"}]}