{"id":733157,"url":"https://alion.io/job/celerocommunications-principal-pll-design-engineer","title":"Principal PLL Design Engineer","company":{"id":668982,"name":"Celero Communications","domain":"celerocommunications.com","url":"https://alion.io/company/celerocommunications","size_band":"201-500","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Greenhouse","truth_index":{"grade":"B","score":80,"open_postings":5,"ghost_share":0,"stale_share":0.8,"repost_share":0,"time_to_fill_p50_days":35,"computed_at":"2026-11-01T06:10:25Z"}},"role":"Industrial Engineering","role_family":"Industrial Engineering","seniority":"lead","employment_type":null,"work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Irvine, United States"],"countries":["US"],"hiring_countries":[],"hiring_countries_total":0,"salary":{"min":150000,"max":250000,"currency":"USD","period":"year","gross":null,"usd_annual":250000},"salary_estimate":null,"experience_years_min":5,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"Cadence Virtuoso","optional":false},{"name":"MATLAB","optional":false}],"status":"live","first_seen_at":"2026-04-06T23:05:29Z","employer_posted_date":"2026-09-29","last_verified_at":"2026-11-01T12:24:25Z","board_verified":true,"closed_at":null,"days_open":208,"trust":{"level":"stale","repost_count":0,"flags":["stale"],"days_open":208},"description":"Are you a PLL Design Engineer passionate about developing the high-speed clocking technology that will power the next generation of AI infrastructure? Join our fast-growing semiconductor startup and help deliver disruptive High-Speed Interconnect solutions for tomorrow's optical networks.\nWe are seeking a High-Speed CMOS PLL Analog Design Engineer to play a key role in the architecture and design of advanced clocking circuits for next-generation optical transceivers, high-speed SerDes, and high-performance ADC/DAC systems. In this role, you will architect and design state-of-the-art PLLs for industry-leading transceivers, working alongside a world-class team to solve some of the most challenging mixed-signal design problems in advanced CMOS technologies. This is an opportunity to make a significant technical impact while helping build groundbreaking products from the ground up.\nLocations: Irvine, CA (HQ) | San Jose, CA | Vancouver, BC | Ottawa, ON\nWhat You Will Do:\nUnderstand trade-offs between different PLL topologies (e.g., integer-N, fractional-N, all-digital/ADPLL) to meet specifications for power, area, jitter, and frequency range\nArchitect, design and simulate analog/mixed-signal PLL building blocks (VCOs, charge pumps, dividers, PFDs, Loop Filters) at transistor level using tools like Cadence Virtuoso and Spectre\nAddress challenges in advanced node technologies, such as self-heating, electromigration, voltage-controlled oscillator (VCO) linearization and device-level noise optimization\nSupervise and verify layouts produced by layout engineers to ensure floorplanning, matching, and parasitic minimization using advanced node technologies\nBe responsible for PLL bring up in the lab, conducting performance characterization using state-of-the-art lab equipment\nConduct comprehensive system-level simulations and validation for PLL integration into advanced transceiver technologies\nWhat You Will Bring: \nMaster’s degree and/or PhD in Electrical Engineering or related fields with 5+ years of relevant experience in PLL design, and production level tape-out experience\nMust have extensive experience with advanced node technologies (16nm/12nm, 7nm, 5nm, 3nm, 2nm processes)\nDeep understanding of phase noise analysis, VCO design, LDOs and supporting circuitry associated with PLLs\nProficient in cadence virtuoso, electromagnetic simulator (e.g., EMX/HFSS), and MATLAB for system-level modelling\nStrong communication and documentation skills\nAnnual Base Salary Range for US: $150,000 - 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