{"id":3190995,"url":"https://alion.io/job/celestica-sr-fpga-engineer","title":"Sr. FPGA Engineer","company":{"id":58064,"name":"Celestica","domain":"celestica.com","url":"https://alion.io/company/celestica","size_band":"1001-5000","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"SuccessFactors","truth_index":null},"role":"Hardware","role_family":"Hardware","seniority":"senior","employment_type":null,"work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Shanghai, China"],"countries":["CN"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":{"min_usd":38000,"max_usd":89000,"period":"year","method":"role_seniority_country_remote_cell","sample_n":8},"experience_years_min":10,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"C++","optional":false},{"name":"Siemens ModelSim","optional":false},{"name":"SystemVerilog","optional":false},{"name":"UVM","optional":false},{"name":"Verilog","optional":false},{"name":"Xilinx Vivado","optional":false},{"name":"Python","optional":true}],"status":"closed","first_seen_at":"2026-09-25T00:00:00Z","employer_posted_date":"2026-09-25","last_verified_at":"2026-10-27T05:48:41Z","board_verified":false,"closed_at":"2026-10-27T05:48:41Z","days_open":32,"trust":{"level":"not_scored","repost_count":null,"flags":[],"days_open":32},"description":"Req ID: 140067\nRegion: Asia\nCountry: China\nState/Province: Shanghai\nCity: Shanghai\nJob Description:\nThe FPGA/CPLD engineer will play a key role in designing, implementing, and validating FPGA/CPLD-based solutions for data center server, storage, and switching platforms.\nThe role involves defining system FPGA/CPLD architecture, technical proposal and part selection, writing RTL code, running simulations, FPGA/CPLD schematic and PCB design review and validating designs on hardware. You will be responsible for optimizing designs to meet system requirements and working closely with hardware and software engineers to ensure full integration.\nThis position works in a cross-functional team with designers, customers, and project leaders to ensure robust and high-quality product development. The FPGA/CPLD engineer will also help improve designs based on feedback from areas such as manufacturing, reliability, and testing.\nJob Responsibilities:\nWork closely with system architecture, hardware designer and software designer to understand/define the architecture requirements \nCreate the design specification, test plans, and reports to ensure design traceability.\nCooperate with hardware engineer on the logic part schematic design /review etc. \nOn-time delivery of the RTL design and module-level verification and test case definition \nPerform pre-synthesis and post-synthesis simulation and validation.\nDrive the entire back-end design flow including design constraints, floor-plan and timing analysis. \nLead debugging and failure analysis efforts during FPGA/CPLD on-board validation.\nCollaborate with peers including different function team to ensure the successful delivery of high-performance systems\nAs a mentor to junior engineers, provide training and technical guidance.\nProvide accurate and timely project schedule estimates, meet project milestone schedule\nJob Requirement:\nBachelors or master's in computer science, Communication and System Engineering, Electrical Engineering or related fields\nBSEE with 10+ years of FPGA/CPLD experience or MSEE with 5+ years of experience, familiar with Xilinx and Intel(Altera)FPGA and Lattice CPLD/FPGA etc.\nIn depth knowledge with Verilog, System Verilog, RTL design, FPGA/CPLD design, and FPGA/CPLD design tools (eg. ISE, Vivado, Quartuse-II, Diamond, Modelsim etc.) \nIn depth knowledge with high speed serial protocols such as PCIe/USB/Ethernet/DDR/LVDS; \nFamiliar with SPI, eSPI, I2C, UART, LPC, MDIO etc. low speed interface. \nFamiliar with UVM constrained random coverage driven concepts, assertion based verification and functional coverage techniques.\nProficient in understanding hardware schematics and PCB designs for FPGA/CPLD pinout constraints and on-board validation.\nProficient in using oscilloscopes, multimeters, logic analyzers, and various hardware debugging and testing tools.\nExcellent problem solving and hands-on debugging skills \nExcellent communications skills and well English speaking/writing ability \nStrong inter -personal skills and ability to understand customer needs, expectations and perspective \nDemonstrated ability to multi-task on multiple projects\nAdditional Prefer Requirement:\nIn depth knowledge with data center server, storage, and switching platforms architecture, with expertise in FPGA/CPLD roles inside the system, FPGA/CPLD part selection, and technical proposal development.\nFamiliar with hardware development processes with extensive experience in hardware design, bring-up, and troubleshooting, proficient in Intel/AMD X86 CPU architecture and power-up sequencing etc.\nIn depth knowledge with secure boot design principles and implementation, providing suitable secure boot solutions for different systems.\nProficient in C/C++, with experience in FPGA/CPLD feature software driver development and verification, familiar with MicroBlaze, Nios-II, or MCU development is a plus.\nProficient in Shell/Python development, customizing scripts based on system requirements for testing purposes.\nCelestica is an equal opportunity employer. All qualified applicants will receive consideration for employment and will not be discriminated against on any protected status (including race, religion, national origin, gender, sexual orientation, age, marital status, veteran or disability status or other characteristics protected by law).\nAt Celestica we are committed to fostering an inclusive, accessible environment, where all employees and customers feel valued, respected and supported. Special arrangements can be made for candidates who need it throughout the hiring process. Please indicate your needs and we will work with you to meet them.\nCOMPANY OVERVIEW:\nCelestica (NYSE, TSX: CLS) enables the world’s best brands. Through our recognized customer-centric approach, we partner with leading companies in Aerospace and Defense, Communications, Enterprise, HealthTech, Industrial, Capital Equipment and Energy to deliver solutions for their most complex challenges. As a leader in design, manufacturing, hardware platform and supply chain solutions, Celestica brings global expertise and insight at every stage of product development - from drawing board to full-scale production and after-market services for products from advanced medical devices, to highly engineered aviation systems, to next-generation hardware platform solutions for the Cloud.\nHeadquartered in Toronto, with talented teams spanning 40+ locations in 13 countries across the Americas, Europe and Asia, we imagine, develop and deliver a better future with our customers.\nCelestica would like to thank all applicants, however, only qualified applicants will be contacted.\nCelestica does not accept unsolicited resumes from recruitment agencies or fee based recruitment services.","description_format":"text","description_chars":5749,"description_truncated":false,"requirements":{"experience_years_min":10,"management_years_min":null,"team_size_min":null,"manages_managers":false,"education":{"level":"bachelor","optional":false},"security_clearance":false,"languages":[{"language":"English","level":"All levels","optional":false}]},"benefits":[],"hiring_locations":[],"hiring_excludes":[],"relocation_offered":false,"industries":["Electronics Manufacturing"],"lifecycle":[{"event":"open","at":"2026-10-24T01:29:00Z"},{"event":"close","at":"2026-10-27T05:48:41Z"}],"visa":[],"liveness":null,"pay":null,"html_url":"https://alion.io/job/celestica-sr-fpga-engineer","json_url":"https://alion.io/job/celestica-sr-fpga-engineer.json","meta":{"generated_at":"2026-10-27T06:44:12Z","cache_seconds":300,"methodology":"https://alion.io/methodology","terms":"https://alion.io/terms","contact":"https://alion.io/contact","api":"https://alion.io/developers","about":"Alion is a live layer of people, companies and AI agents: who they are, whether they are real and active right now, what they do and how to work with them, readable by people and by agents and paid per call.","catalog":"https://alion.io/catalog.json","usage":{"tier":"crawler_verified","counted_by":"address","units_charged":1,"used_today":7053,"day_limit":null,"remaining_today":null,"minute_limit":300,"resets_at":"2026-10-28T00:00:00Z"}},"offers":[{"id":"company.slices","title":"One company in depth, by slice","status":"live","price":{"credits":0.02,"usd":0.002,"plus_per_slice":{"credits":0.05,"usd":0.005}},"unit":"per company, plus each slice with data","note":"the employer in depth","call":{"mcp_tool":"get_company","arguments":{"id":58064},"rest":"https://alion.io/mcp/rest/get_company?id=58064"},"human":"https://alion.io/catalog?offer=company.slices&for=job%2Fcelestica-sr-fpga-engineer"},{"id":"market.stats","title":"A market slice: pay, demand and time to fill","status":"live","price":{"credits":1,"usd":0.1},"unit":"per slice","note":"pay, demand and time to fill for this role and place","call":{"mcp_tool":"market_stats"},"human":"https://alion.io/catalog?offer=market.stats&for=job%2Fcelestica-sr-fpga-engineer"},{"id":"job.search","title":"Open jobs by role, technology, place, pay and visa","status":"live","price":{"credits":0.02,"usd":0.002},"unit":"per posting in a list","note":"similar open postings","call":{"mcp_tool":"search_jobs"},"human":"https://alion.io/catalog?offer=job.search&for=job%2Fcelestica-sr-fpga-engineer"},{"id":"company.verify","title":"Is this company real and active right now","status":"pilot","price":null,"unit":"per company","request":{"url":"https://alion.io/catalog/request","method":"POST","body":"{\"offer\": \"company.verify\", \"for\": \"job/celestica-sr-fpga-engineer\", \"note\": \"what you need it for\"}"},"human":"https://alion.io/catalog?offer=company.verify&for=job%2Fcelestica-sr-fpga-engineer"}]}