{"id":17045,"url":"https://alion.io/job/cerebras-lead-rtl-design-engineer","title":"Lead RTL Design Engineer","company":{"id":31,"name":"Cerebras Systems","domain":"cerebras.ai","url":"https://alion.io/company/cerebras-systems","size_band":"1001-5000","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Ashby","truth_index":{"grade":"B","score":74,"open_postings":25,"ghost_share":0,"stale_share":0.84,"repost_share":0,"time_to_fill_p50_days":86,"computed_at":"2026-10-19T05:45:15Z"}},"role":"Hardware","role_family":"Hardware","seniority":"lead","employment_type":"full_time","work_mode":"hybrid","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Sunnyvale, United States"],"countries":["US"],"hiring_countries":[],"hiring_countries_total":0,"salary":{"min":200000,"max":299000,"currency":"USD","period":"year","gross":null,"usd_annual":299000},"salary_estimate":null,"experience_years_min":8,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"AI Agents","optional":false},{"name":"Cerebras","optional":false},{"name":"Edge AI","optional":false},{"name":"Machine Learning","optional":false},{"name":"OpenAI","optional":false},{"name":"Python","optional":false},{"name":"TCP/IP","optional":false}],"status":"live","first_seen_at":"2026-07-23T20:12:26Z","employer_posted_date":"2026-08-07","last_verified_at":"2026-10-19T03:09:11Z","board_verified":true,"closed_at":null,"days_open":87,"trust":{"level":"ok","repost_count":null,"flags":[],"days_open":87},"description":"Cerebras Systems builds the world's largest AI chip, 56 times larger than GPUs. This architecture allows Cerebras to deliver industry-leading training and inference speeds; over 10 times faster than GPU-based hyperscale cloud inference services. \nThis order of magnitude increase in speed is transforming the user experience of AI applications, unlocking real-time iteration and increasing intelligence via additional agentic computation.\nCerebras works with the leading model labs, global enterprises, and cutting-edge AI-native startups. OpenAI recently announced a multi-year partnership with Cerebras, to deploy 750 megawatts of scale, transforming key workloads with ultra high-speed inference.\nAbout The Role\nAs a lead front-end design engineer, you will be a key part of the world-class team designing and developing the next generations of the Cerebras Wafer Scale Engine (WSE).\nThis role requires deep expertise in RTL design and integration, with a strong focus on delivering high-performance, power-efficient, and scalable solutions. The role also requires close collaboration and management of external ASIC vendor. You will collaborate closely with the design verification, physical design, software and system teams to bring innovative semiconductor architectures from concept to production, addressing the unique challenges of building WSE systems.\nResponsibilities\nDrive all aspects of chip design, including Functional Specification, Micro-architecture, RTL development, Synthesis.\n\nManaging external ASIC vendor through product development cycle.\n\nWork closely with PD team members for design closure to meet PPA goals.\n\nWork closely with Design verification and DFT teams for achieving the best functional and test coverage.\n\nWork with software and system teams to understand opportunities to deliver optimal performance and feature set for the product.\n\nDebug silicon-level functional, timing, and power issues during bring up.\n\nRequirements\nMaster’s degree in Computer Science, Electrical Engineering, or equivalent.\n\nCan work in a hybrid work environment.\n\n8-15 years of experience in delivering complex, high performance high quality RTL designs.\n\nExperience with Front End Chip integration and third-party IP integration.\n\nDemonstrated experience in networking, high-performance computing, machine learning or related fields.\n\nProven track record of multiple silicon success.\n\nExperience collaborating and managing external vendors.\n\nExperience with designing/integrating high speed IO.\n\nNetworking stack experience including TCP/IP, RDMA and Ethernet.\n\nKnowledge of PCIe, CPU interfaces and Serdes technology.\n\nWorking knowledge of scripting tools : Python, TCL.\n\nAssets\nExperience with FPGA development toolchain, including Place and Route, Floor planning and Timing Analysis is a plus.\n\nThe base salary range for this position is $200,000 to $299,000 annually. Actual compensation may include bonus and equity, and will be determined based on factors such as experience, skills, and qualifications.\nWhy Join Cerebras\nPeople who are serious about software make their own hardware. At Cerebras, we have built a breakthrough architecture that is unlocking new opportunities for the AI industry. With dozens of model releases and rapid growth, we’ve reached an inflection point in our business. Members of our team tell us there are five main reasons they joined Cerebras:\nBuild a breakthrough AI platform beyond the constraints of the GPU.\n\nPublish and open source their cutting-edge AI research.\n\nWork on one of the fastest AI supercomputers in the world.\n\nEnjoy job stability with startup vitality.\n\nOur simple, non-corporate work culture that respects individual beliefs.\n\nFind out more about what it's like to work at Cerebras here!\nApply today and become part of the forefront of groundbreaking advancements in AI!\nCerebras Systems is committed to creating an equal and diverse environment and is proud to be an equal opportunity employer. We celebrate different backgrounds, perspectives, and skills. We believe inclusive teams build better products and companies. We try every day to build a work environment that empowers people to do their best work through continuous learning, growth and support of those around them.\nThis website or its third-party tools process personal data. For more details, click here to review our CCPA disclosure notice.","description_format":"text","description_chars":4380,"description_truncated":false,"requirements":{"experience_years_min":8,"management_years_min":null,"team_size_min":null,"manages_managers":false,"education":{"level":"master","optional":false},"security_clearance":false,"languages":[]},"benefits":["Continuous learning","Equity","Hybrid work"],"hiring_locations":[{"name":"United States","iso":"US","kind":"country"}],"hiring_excludes":[],"relocation_offered":false,"industries":["Processors, MCUs & AI Chips","Servers & Data Center Hardware","AI Compute & Inference","AI Chips & Accelerators"],"lifecycle":[{"event":"open","at":"2026-07-23T20:12:26Z"}],"visa":[{"country":"US","licensed_sponsor":true,"evidence":"H-1B filings in 12 months: 43 · green card filings: 5","filings_12m":43,"filings_prev_12m":27,"green_card_filings_12m":5,"median_offered_wage_usd":200938,"route":null,"cap_exempt":false,"checked_at":"2026-10-15T11:24:14+00:00","sources":["US Department of Labor: LCA disclosure data (H-1B, H-1B1, E-3)","US Department of Labor: PERM disclosure data (green cards)"],"filings_for_role_12m":6}],"liveness":{"score":24,"band":"cold","label":"Long shot","p_open":1,"p_active":0.544,"p_room":0.44,"age_days":87,"expected_fill_days":86,"reasons":["conf:2","stale_co","velocity","win:tail","crowd:brand"],"computed_at":"2026-10-19T05:45:15Z"},"pay":{"stated_usd_annual":299000,"is_top_pay":true},"html_url":"https://alion.io/job/cerebras-lead-rtl-design-engineer","json_url":"https://alion.io/job/cerebras-lead-rtl-design-engineer.json","meta":{"generated_at":"2026-10-19T06:23:41Z","cache_seconds":300,"methodology":"https://alion.io/methodology","terms":"https://alion.io/terms","contact":"https://alion.io/contact","api":"https://alion.io/developers","about":"Alion is a live layer of people, companies and AI agents: who they are, whether they are real and active right now, what they do and how to work with them, readable by people and by agents and paid per call.","catalog":"https://alion.io/catalog.json","usage":{"tier":"crawler_verified","counted_by":"address","units_charged":1,"used_today":4016,"day_limit":null,"remaining_today":null,"minute_limit":300,"resets_at":"2026-10-20T00:00:00Z"}},"offers":[{"id":"company.slices","title":"One company in depth, by slice","status":"live","price":{"credits":0.02,"usd":0.002,"plus_per_slice":{"credits":0.05,"usd":0.005}},"unit":"per company, plus each slice with data","note":"the employer in depth","call":{"mcp_tool":"get_company","arguments":{"id":31},"rest":"https://alion.io/mcp/rest/get_company?id=31"},"human":"https://alion.io/catalog?offer=company.slices&for=job%2Fcerebras-lead-rtl-design-engineer"},{"id":"market.stats","title":"A market slice: pay, demand and time to fill","status":"live","price":{"credits":1,"usd":0.1},"unit":"per slice","note":"pay, demand and time to fill for this role and place","call":{"mcp_tool":"market_stats"},"human":"https://alion.io/catalog?offer=market.stats&for=job%2Fcerebras-lead-rtl-design-engineer"},{"id":"job.search","title":"Open jobs by role, technology, place, pay and visa","status":"live","price":{"credits":0.02,"usd":0.002},"unit":"per posting in a list","note":"similar open postings","call":{"mcp_tool":"search_jobs"},"human":"https://alion.io/catalog?offer=job.search&for=job%2Fcerebras-lead-rtl-design-engineer"},{"id":"company.verify","title":"Is this company real and active right now","status":"pilot","price":null,"unit":"per company","request":{"url":"https://alion.io/catalog/request","method":"POST","body":"{\"offer\": \"company.verify\", \"for\": \"job/cerebras-lead-rtl-design-engineer\", \"note\": \"what you need it for\"}"},"human":"https://alion.io/catalog?offer=company.verify&for=job%2Fcerebras-lead-rtl-design-engineer"}]}