{"id":1191576,"url":"https://alion.io/job/cesiumastro-fpga-engineer-i-2","title":"FPGA Engineer I","company":{"id":5315,"name":"CesiumAstro","domain":"cesiumastro.com","url":"https://alion.io/company/cesiumastro","size_band":"1001-5000","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Lever","truth_index":{"grade":"B","score":77,"open_postings":23,"ghost_share":0,"stale_share":0.913,"repost_share":0,"time_to_fill_p50_days":54,"computed_at":"2026-09-25T05:45:01Z"}},"role":"Hardware","role_family":"Hardware","seniority":"junior","employment_type":"full_time","work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Melbourne, United States"],"countries":["US"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":{"min_usd":69000,"max_usd":140000,"period":"year","method":"role_seniority_country_remote_cell","sample_n":209},"experience_years_min":null,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"HDL Coder","optional":true},{"name":"Siemens ModelSim","optional":true},{"name":"Verilog","optional":true},{"name":"VHDL","optional":true},{"name":"Xilinx Vivado","optional":true}],"status":"live","first_seen_at":"2026-09-24T14:42:14Z","employer_posted_date":"2026-09-24","last_verified_at":"2026-09-25T22:18:42Z","board_verified":true,"closed_at":null,"days_open":1,"trust":{"level":"ok","repost_count":null,"flags":[],"days_open":1},"description":"We are looking to add an FPGA Engineer I to our team. If you enjoy working in a startup environment, and are passionate about developing leading-edge hardware for satellites, spacecraft, and aerospace systems, we would like to hear from you.\nIn this position, you will contribute to the development of FPGA circuits and systems through all phases of the development process. The ideal candidate will have experience in FPGA design, verification, test, and deployment at the HDL level. FPGA HDL designs will include high-speed serial interfaces and data streams, digital processing cores, multiple clocks and clock domains, and management interfaces. Testing, validation, and verification will also be central tasks for any FPGA design. Experience in digital signal processing or board-level hardware design is also desirable.\nJOB REQUIREMENTS AND MINIMUM QUALIFICATIONS\nBachelor of Science (BS) or Master of Science (MS) degree in Electrical Engineering or Computer Engineering from an accredited university or institution.\nUniversity experience in the design, analysis, and implementation of FPGA systems at the HDL level. \nExpertise in FPGA design and verification (Verilog/VHDL, HDL coder, Xilinx’s Vivado, Modelsim, etc.).\nHands-on experience with lab instruments such as digital oscilloscopes, spectrum analyzers, RF signal generators, and vector signal analyzers.\nExcellent written and verbal communication skills.\nPREFERRED EXPERIENCE\nAerospace design and qualification.\nWorst-case analysis, failure method and criticality analyses, and reliability analysis.\nExperience with board-level hardware design.\nFamiliarity with communications systems, such as digital signal processing.","description_format":"text","description_chars":1686,"description_truncated":false,"requirements":{"experience_years_min":null,"management_years_min":null,"team_size_min":null,"manages_managers":false,"education":{"level":"bachelor","optional":false},"security_clearance":false,"languages":[]},"benefits":[],"hiring_locations":[],"hiring_excludes":[],"relocation_offered":false,"industries":["Space & Aerospace","Satellite Communications"],"lifecycle":[{"event":"open","at":"2026-09-24T16:58:56Z"}],"liveness":{"score":63,"band":"ok","label":"Likely open","p_open":1,"p_active":0.632,"p_room":1,"age_days":0,"expected_fill_days":54,"reasons":["conf:0","stale_co","velocity","win:early","comp:junior,brand"],"computed_at":"2026-09-25T05:45:01Z"},"pay":null,"html_url":"https://alion.io/job/cesiumastro-fpga-engineer-i-2","json_url":"https://alion.io/job/cesiumastro-fpga-engineer-i-2.json","meta":{"generated_at":"2026-09-26T03:33:02Z","cache_seconds":300,"methodology":"https://alion.io/methodology","terms":"https://alion.io/terms","contact":"https://alion.io/contact","api":"https://alion.io/developers","usage":{"tier":"crawler","counted_by":"address","units_charged":1,"used_today":3784,"day_limit":5000,"remaining_today":1216,"minute_limit":60,"resets_at":"2026-09-27T00:00:00Z"}}}