{"id":1159518,"url":"https://alion.io/job/cesiumastro-fpga-verification-engineer-ii-2","title":"FPGA Verification Engineer II","company":{"id":5315,"name":"CesiumAstro","domain":"cesiumastro.com","url":"https://alion.io/company/cesiumastro","size_band":"1001-5000","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Lever","truth_index":{"grade":"B","score":84,"open_postings":40,"ghost_share":0,"stale_share":0.625,"repost_share":0,"time_to_fill_p50_days":48,"computed_at":"2026-10-22T06:10:10Z"}},"role":"Hardware","role_family":"Hardware","seniority":"middle","employment_type":"full_time","work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Austin, United States"],"countries":["US"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":{"min_usd":92000,"max_usd":178000,"period":"year","method":"role_seniority_country_remote_cell","sample_n":609},"experience_years_min":2,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"C++","optional":false},{"name":"CI/CD","optional":false},{"name":"Linux","optional":false},{"name":"MATLAB","optional":false},{"name":"Python","optional":false},{"name":"QEMU","optional":false},{"name":"SystemC","optional":false},{"name":"SystemVerilog","optional":false},{"name":"UVM","optional":false},{"name":"Verilog","optional":false},{"name":"VHDL","optional":false}],"status":"live","first_seen_at":"2026-09-23T17:13:25Z","employer_posted_date":"2026-09-23","last_verified_at":"2026-10-22T22:46:01Z","board_verified":true,"closed_at":null,"days_open":29,"trust":{"level":"ok","repost_count":null,"flags":[],"days_open":29},"description":"We are looking to add an FPGA Verification Engineer II to our team. If you enjoy working in a startup environment and are passionate about developing leading-edge phased arrays for satellites, spacecraft, and aerospace systems, we would like to hear from you.\nJOB DUTIES AND RESPONSIBILITIES\nContribute to the evaluation and technical implementation of FPGA and digital design simulation, verification and emulation infrastructure.\nContribute to the development, maintenance and phased deployment of continuous integration and regression testing infrastructure.\nDevelop state-of-the-art UVMf-based top-level and module-level testbenches using block-to-top best practices for reusability, including both control and data plane stimulation using VIP & System Verilog DPI-C integration with existing MATLAB and Python numerical models.\nLead the development of reusable custom VIP modules.\nWork closely with the engineering and senior leadership teams to train and mentor engineers at all experience levels on UVMf testbench usage and modern approaches to FPGA/digital design. Work with the modeling and scientific staff to implement DPI-C dataplane verification interfaces into existing MATLAB and Python models.\nAid the Lead Verification Engineer in evaluating current processes regarding FPGA and digital design with a focus on Xilinx TLM models and QEMU-RP integration.\nWork closely with vendors to define requirements of future simulation model deliverables.\nMaintain up-to-date knowledge of industry best-practices regarding FPGA and digital design methodologies.\nWork closely with the engineering leadership team to evaluate and non-disruptively implement process improvements.\nJOB REQUIREMENTS AND MINIMUM QUALIFICATIONS\nA Bachelor of Science (BS) or Master of Science (MS) degree in Computer Science, Electrical Engineering, or Computer Engineering.\nMinimum of 2 years of industry experience in verification and automation.\nKnowledge of FPGA digital design verification techniques including VHDL, Verilog, SystemVerilog, C/C++, SystemC, UVM/UVMf, DPI-C, TLM, Formal CDC and functional analysis, QEMU and VIP.\nUnderstanding of digital design automation infrastructure, including CI, regression testing and HIL testing.\nCompetency with Linux.\nKnowledge of vendor-provided FPGA development tools with a focus on Xilinx tools.","description_format":"text","description_chars":2327,"description_truncated":false,"requirements":{"experience_years_min":2,"management_years_min":null,"team_size_min":null,"manages_managers":false,"education":{"level":"bachelor","optional":false},"security_clearance":false,"languages":[]},"benefits":[],"hiring_locations":[],"hiring_excludes":[],"relocation_offered":false,"industries":["Embedded & Electronics Design","Satellite Communications","RF & Wireless Hardware"],"lifecycle":[{"event":"open","at":"2026-09-23T23:04:14Z"}],"visa":[{"country":"US","licensed_sponsor":true,"evidence":"H-1B filings in 12 months: 2","filings_12m":2,"filings_prev_12m":0,"green_card_filings_12m":0,"median_offered_wage_usd":152500,"route":null,"cap_exempt":false,"checked_at":"2026-10-15T11:24:14+00:00","sources":["US Department of Labor: LCA disclosure data (H-1B, H-1B1, E-3)"],"filings_for_role_12m":0}],"liveness":{"score":51,"band":"ok","label":"Likely open","p_open":1,"p_active":0.568,"p_room":0.9,"age_days":28,"expected_fill_days":48,"reasons":["conf:2","stale_co","velocity","win:mid","comp:brand"],"computed_at":"2026-10-22T06:10:10Z"},"pay":null,"html_url":"https://alion.io/job/cesiumastro-fpga-verification-engineer-ii-2","json_url":"https://alion.io/job/cesiumastro-fpga-verification-engineer-ii-2.json","meta":{"generated_at":"2026-10-23T01:35:49Z","cache_seconds":300,"methodology":"https://alion.io/methodology","terms":"https://alion.io/terms","contact":"https://alion.io/contact","api":"https://alion.io/developers","about":"Alion is a live layer of people, companies and AI agents: who they are, whether they are real and active right now, what they do and how to work with them, readable by people and by agents and paid per call.","catalog":"https://alion.io/catalog.json","usage":{"tier":"crawler_verified","counted_by":"address","units_charged":1,"used_today":2653,"day_limit":null,"remaining_today":null,"minute_limit":300,"resets_at":"2026-10-24T00:00:00Z"}},"offers":[{"id":"company.slices","title":"One company in depth, by slice","status":"live","price":{"credits":0.02,"usd":0.002,"plus_per_slice":{"credits":0.05,"usd":0.005}},"unit":"per company, plus each slice with data","note":"the employer in depth","call":{"mcp_tool":"get_company","arguments":{"id":5315},"rest":"https://alion.io/mcp/rest/get_company?id=5315"},"human":"https://alion.io/catalog?offer=company.slices&for=job%2Fcesiumastro-fpga-verification-engineer-ii-2"},{"id":"market.stats","title":"A market slice: pay, demand and time to fill","status":"live","price":{"credits":1,"usd":0.1},"unit":"per slice","note":"pay, demand and time to fill for this role and place","call":{"mcp_tool":"market_stats"},"human":"https://alion.io/catalog?offer=market.stats&for=job%2Fcesiumastro-fpga-verification-engineer-ii-2"},{"id":"job.search","title":"Open jobs by role, technology, place, pay and visa","status":"live","price":{"credits":0.02,"usd":0.002},"unit":"per posting in a list","note":"similar open postings","call":{"mcp_tool":"search_jobs"},"human":"https://alion.io/catalog?offer=job.search&for=job%2Fcesiumastro-fpga-verification-engineer-ii-2"},{"id":"company.verify","title":"Is this company real and active right now","status":"pilot","price":null,"unit":"per company","request":{"url":"https://alion.io/catalog/request","method":"POST","body":"{\"offer\": \"company.verify\", \"for\": \"job/cesiumastro-fpga-verification-engineer-ii-2\", \"note\": \"what you need it for\"}"},"human":"https://alion.io/catalog?offer=company.verify&for=job%2Fcesiumastro-fpga-verification-engineer-ii-2"}]}