{"id":3166338,"url":"https://alion.io/job/cesiumastro-principal-asic-design-engineer-chip-lead","title":"Principal ASIC Design Engineer - Chip Lead","company":{"id":5315,"name":"CesiumAstro","domain":"cesiumastro.com","url":"https://alion.io/company/cesiumastro","size_band":"1001-5000","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Lever","truth_index":{"grade":"A","score":85,"open_postings":42,"ghost_share":0,"stale_share":0.619,"repost_share":0,"time_to_fill_p50_days":47,"computed_at":"2026-10-26T05:57:25Z"}},"role":"Hardware","role_family":"Hardware","seniority":"lead","employment_type":"full_time","work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Aliso Viejo, United States"],"countries":["US"],"hiring_countries":[],"hiring_countries_total":0,"salary":{"min":15000,"max":199000,"currency":"USD","period":"year","gross":null,"usd_annual":15000},"salary_estimate":null,"experience_years_min":10,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"Formal Verification","optional":false},{"name":"SystemVerilog","optional":false},{"name":"UVM","optional":false},{"name":"Verilog","optional":false}],"status":"live","first_seen_at":"2026-10-02T18:21:05Z","employer_posted_date":"2026-10-02","last_verified_at":"2026-10-26T12:02:42Z","board_verified":true,"closed_at":null,"days_open":23,"trust":{"level":"ok","repost_count":null,"flags":[],"days_open":23},"description":"We are looking to add a Principal ASIC Design Engineer - Chip Lead for our next generation industry leading high speed mixed signal/DSP projects. We are specifically looking for someone with cradle-to-grave experience who knows all levels of large, high-speed communications chip design. The ideal candidate will have knowledge in all or most of the following areas: digital communications systems, DSP, ASIC microacrchitecture, analog IP integration, embedded processors, high level verification, RTL design with multiple asynchronous clock domains, timing analysis, DFT, backend flow, chip bring up, debug, lab testing, and transitioning a product from first sample through release to volume production.\nJOB REQUIREMENTS AND MINIMUM QUALIFICATIONS\nMaster’s in Engineering with a minimum of 10 years of experience. \nExperience with the IC/ASIC development flow from concept through production release of silicon.\nExperience in defining and using advanced front-end design flows from system simulation through RTL implementation, verification, synthesis, and interfacing with a backend team.\nExperience in high speed analog block integration into digital logic.\nThe candidate must have a well-developed ability to analyze specifications at the architecture and micro-architecture level to identify design improvements.\nExcellent program management, people management, and project tracking skills.\nExperience with customer communications and marketing/sales interactions.\nExperience with ASIC verification using random constraint coverage driven verification methodology like UVM, VMM, OVM or SPECMAN.\nFluency with Verilog and System Verilog, experience with synthesis, formal verification, and STA flow set up. Experience with low power design flows highly desirable.\nExperience in DSP block implementation highly desirable.","description_format":"text","description_chars":1824,"description_truncated":false,"requirements":{"experience_years_min":10,"management_years_min":null,"team_size_min":null,"manages_managers":false,"education":{"level":"master","optional":false},"security_clearance":false,"languages":[]},"benefits":[],"hiring_locations":[],"hiring_excludes":[],"relocation_offered":false,"industries":["Embedded & Electronics Design","Satellite Communications","RF & Wireless Hardware"],"lifecycle":[{"event":"open","at":"2026-10-23T17:28:09Z"}],"visa":[{"country":"US","licensed_sponsor":true,"evidence":"H-1B filings in 12 months: 2","filings_12m":2,"filings_prev_12m":0,"green_card_filings_12m":0,"median_offered_wage_usd":152500,"route":null,"cap_exempt":false,"checked_at":"2026-10-15T11:24:14+00:00","sources":["US Department of Labor: LCA disclosure data (H-1B, H-1B1, E-3)"],"filings_for_role_12m":0}],"liveness":{"score":57,"band":"ok","label":"Likely open","p_open":1,"p_active":0.632,"p_room":0.9,"age_days":23,"expected_fill_days":47,"reasons":["conf:2","stale_co","velocity","win:mid","comp:brand"],"computed_at":"2026-10-26T05:57:25Z"},"pay":{"stated_usd_annual":15000,"is_top_pay":false},"html_url":"https://alion.io/job/cesiumastro-principal-asic-design-engineer-chip-lead","json_url":"https://alion.io/job/cesiumastro-principal-asic-design-engineer-chip-lead.json","meta":{"generated_at":"2026-10-26T13:12:53Z","cache_seconds":300,"methodology":"https://alion.io/methodology","terms":"https://alion.io/terms","contact":"https://alion.io/contact","api":"https://alion.io/developers","about":"Alion is a live layer of people, companies and AI agents: who they are, whether they are real and active right now, what they do and how to work with them, readable by people and by agents and paid per call.","catalog":"https://alion.io/catalog.json","usage":{"tier":"crawler_verified","counted_by":"address","units_charged":1,"used_today":18385,"day_limit":null,"remaining_today":null,"minute_limit":300,"resets_at":"2026-10-27T00:00:00Z"}},"offers":[{"id":"company.slices","title":"One company in depth, by slice","status":"live","price":{"credits":0.02,"usd":0.002,"plus_per_slice":{"credits":0.05,"usd":0.005}},"unit":"per company, plus each slice with data","note":"the employer in depth","call":{"mcp_tool":"get_company","arguments":{"id":5315},"rest":"https://alion.io/mcp/rest/get_company?id=5315"},"human":"https://alion.io/catalog?offer=company.slices&for=job%2Fcesiumastro-principal-asic-design-engineer-chip-lead"},{"id":"market.stats","title":"A market slice: pay, demand and time to fill","status":"live","price":{"credits":1,"usd":0.1},"unit":"per slice","note":"pay, demand and time to fill for this role and place","call":{"mcp_tool":"market_stats"},"human":"https://alion.io/catalog?offer=market.stats&for=job%2Fcesiumastro-principal-asic-design-engineer-chip-lead"},{"id":"job.search","title":"Open jobs by role, technology, place, pay and visa","status":"live","price":{"credits":0.02,"usd":0.002},"unit":"per posting in a list","note":"similar open postings","call":{"mcp_tool":"search_jobs"},"human":"https://alion.io/catalog?offer=job.search&for=job%2Fcesiumastro-principal-asic-design-engineer-chip-lead"},{"id":"company.verify","title":"Is this company real and active right now","status":"pilot","price":null,"unit":"per company","request":{"url":"https://alion.io/catalog/request","method":"POST","body":"{\"offer\": \"company.verify\", \"for\": \"job/cesiumastro-principal-asic-design-engineer-chip-lead\", \"note\": \"what you need it for\"}"},"human":"https://alion.io/catalog?offer=company.verify&for=job%2Fcesiumastro-principal-asic-design-engineer-chip-lead"}]}