Principal Verification Engineer

The Design Verification team is growing and has a need for a top talent, principal level, ASIC functional verification engineer. The position may also involve team or project leadership. In this role, you will be responsible for the development of leading edge verification methodologies for complex high speed digital communication SoCs.

JOB DUTIES AND RESPONSIBILITIES

• Design and implement verification test bench infrastructure and test cases for system, chip and block level verification, using the latest tools and SystemVerilog class libraries such as OVM, UVM, and VMM.
• Implement Pseudo-random and functional coverage verification methodologies.
• Develop functional test and verification plans.
• Work closely with the VLSI Design team to plan and implement design verification strategies.

JOB REQUIREMENTS AND MINIMUM QUALIFICATIONS

• Minimum of 10 years of relevant experience with a Bachelor of Science (BS) degree in Computer Science, Electrical Engineering, or Computer Engineering or related engineering discipline, or a minimum of 8 years of experience with a Masters degree.
• Proficiency in Pseudo-random and functional coverage verification methodologies.
• Strong working knowledge of SystemVerilog and its class libraries such as UVM, OVM or VMM.
• Experience with SVA, PSL, or OVL assertions.
• Excellent written and verbal communication skills.

PREFERRED EXPERIENCE

• Formal model checking tools (e.g. Cadence IFV, Jasper).
• Experience with DSP and digital communications.