{"id":1742548,"url":"https://alion.io/job/cesiumastro-principal-verification-engineer","title":"Principal Verification Engineer","company":{"id":5315,"name":"CesiumAstro","domain":"cesiumastro.com","url":"https://alion.io/company/cesiumastro","size_band":"1001-5000","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Lever","truth_index":{"grade":"B","score":77,"open_postings":25,"ghost_share":0,"stale_share":0.92,"repost_share":0,"time_to_fill_p50_days":48,"computed_at":"2026-10-04T05:45:00Z"}},"role":"Hardware","role_family":"Hardware","seniority":"lead","employment_type":"full_time","work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Aliso Viejo, United States"],"countries":["US"],"hiring_countries":[],"hiring_countries_total":0,"salary":{"min":165000,"max":199000,"currency":"USD","period":"year","gross":null,"usd_annual":199000},"salary_estimate":null,"experience_years_min":10,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"SystemVerilog","optional":false},{"name":"UVM","optional":false}],"status":"live","first_seen_at":"2026-09-28T16:26:10Z","employer_posted_date":"2026-09-28","last_verified_at":"2026-10-05T02:14:55Z","board_verified":true,"closed_at":null,"days_open":6,"trust":{"level":"ok","repost_count":null,"flags":[],"days_open":6},"description":"The Design Verification team is growing and has a need for a top talent, principal level, ASIC functional verification engineer. The position may also involve team or project leadership. In this role, you will be responsible for the development of leading edge verification methodologies for complex high speed digital communication SoCs.\nJOB DUTIES AND RESPONSIBILITIES\nDesign and implement verification test bench infrastructure and test cases for system, chip and block level verification, using the latest tools and SystemVerilog class libraries such as OVM, UVM, and VMM.\nImplement Pseudo-random and functional coverage verification methodologies.\nDevelop functional test and verification plans.\nWork closely with the VLSI Design team to plan and implement design verification strategies.\nJOB REQUIREMENTS AND MINIMUM QUALIFICATIONS\nMinimum of 10 years of relevant experience with a Bachelor of Science (BS) degree in Computer Science, Electrical Engineering, or Computer Engineering or related engineering discipline, or a minimum of 8 years of experience with a Masters degree. \nProficiency in Pseudo-random and functional coverage verification methodologies.\nStrong working knowledge of SystemVerilog and its class libraries such as UVM, OVM or VMM.\nExperience with SVA, PSL, or OVL assertions.\nExcellent written and verbal communication skills.\nPREFERRED EXPERIENCE\nFormal model checking tools (e.g. Cadence IFV, Jasper).\nExperience with DSP and digital communications.","description_format":"text","description_chars":1478,"description_truncated":false,"requirements":{"experience_years_min":10,"management_years_min":null,"team_size_min":null,"manages_managers":false,"education":{"level":"bachelor","optional":false},"security_clearance":false,"languages":[]},"benefits":[],"hiring_locations":[],"hiring_excludes":[],"relocation_offered":false,"industries":["Hardware","Space & Aerospace","Embedded & Electronics Design","Satellite Communications"],"lifecycle":[{"event":"open","at":"2026-10-03T03:49:05Z"}],"visa":[{"country":"US","licensed_sponsor":true,"evidence":"H-1B filings in 12 months: 2","filings_12m":2,"filings_prev_12m":0,"green_card_filings_12m":0,"median_offered_wage_usd":152500,"route":null,"cap_exempt":false,"checked_at":"2026-10-03T21:08:04+00:00","sources":["US Department of Labor: LCA disclosure data (H-1B, H-1B1, E-3)"],"filings_for_role_12m":0}],"liveness":{"score":63,"band":"ok","label":"Likely open","p_open":1,"p_active":0.632,"p_room":1,"age_days":5,"expected_fill_days":48,"reasons":["conf:0","stale_co","velocity","win:early","comp:brand"],"computed_at":"2026-10-04T05:45:00Z"},"pay":{"stated_usd_annual":199000,"is_top_pay":false},"html_url":"https://alion.io/job/cesiumastro-principal-verification-engineer","json_url":"https://alion.io/job/cesiumastro-principal-verification-engineer.json","meta":{"generated_at":"2026-10-05T02:50:10Z","cache_seconds":300,"methodology":"https://alion.io/methodology","terms":"https://alion.io/terms","contact":"https://alion.io/contact","api":"https://alion.io/developers","usage":{"tier":"crawler","counted_by":"address","units_charged":1,"used_today":3898,"day_limit":5000,"remaining_today":1102,"minute_limit":60,"resets_at":"2026-10-06T00:00:00Z"}}}