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Salary
≈ $112k – $205k per year (Estimated)
Location
In office (Austin)
Seniority
Senior · 6+ years exp
Visa
H-1B filings in 12 months: 2
Employment
Full-Time

Confirmed on the employer's own hiring board on Oct 19, 2026. First seen by Alion on Sep 24, 2026. CesiumAstro scores A on the Alion truth index.

Overview
Company
Impact
Profile match
CesiumAstro is an American company founded in Austin in 2017 that builds active phased array communications payloads for satellites, aircraft and defence platforms. Its systems are software-defined and electronically steered, which lets a moving platform track several links at once without mechanical antennas, and the company manufactures them in house rather than integrating third-party subsystems. It sells mainly to defence customers and satellite operators, has raised venture funding from investors including Airbus Ventures and Lightspeed, and operates facilities in Austin, Colorado and the United Kingdom.

We are looking to add a Senior FPGA Engineer to our team. If you enjoy working in a startup environment and are passionate about developing leading-edge hardware for satellites, spacecraft, and aerospace systems, we would like to hear from you.

In this position, you will be responsible for FPGA circuits and systems through all phases of the development process. The ideal candidate will have experience in FPGA design, verification, test, and deployment at the HDL level. FPGA HDL designs will include high-speed serial interfaces and data streams, digital processing cores, multiple clocks and clock domains, and management interfaces. Testing, validation, and verification will also be central tasks for any FPGA design. Experience in digital signal processing or board-level hardware design is also desirable.

The successful candidate will present engineering design review materials to our customers and executive team, as well as participate in proposal-writing efforts. As such, excellent written and verbal communication skills are required.

JOB REQUIREMENTS AND MINIMUM QUALIFICATIONS

  • Bachelor of Science (BS) or Master of Science (MS) degree in Electrical Engineering or Computer Engineering from an accredited university or institution.
  • Minimum of 6 years of industry or university research experience in the design, analysis, and implementation of FPGA systems at the HDL level.
  • Expertise in FPGA design and verification (Verilog/VHDL, HDL coder, Xilinx’s Vivado, Modelsim, etc.).
  • Hands-on experience with lab instruments such as digital oscilloscopes, spectrum analyzers, RF signal generators, and vector signal analyzers.
  • Excellent written and verbal communication skills.

PREFERRED EXPERIENCE

  • Aerospace design and qualification.
  • Worst-case analysis, failure method and criticality analyses, and reliability analysis.
  • Experience with board-level hardware design.
  • Familiarity with communications systems, such as digital signal processing.
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