{"id":2227797,"url":"https://alion.io/job/ciena-asic-synthesis-and-sta-engineer-new-grad","title":"ASIC Synthesis and STA Engineer - New Grad","company":{"id":1996,"name":"Ciena Corporation","domain":"ciena.com","url":"https://alion.io/company/ciena","size_band":"1001-5000","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Workday","truth_index":{"grade":"B","score":77,"open_postings":26,"ghost_share":0,"stale_share":0.923,"repost_share":0,"time_to_fill_p50_days":38,"computed_at":"2026-10-25T05:49:26Z"}},"role":"Hardware","role_family":"Hardware","seniority":"junior","employment_type":"full_time","work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Ottawa, Canada"],"countries":["CA"],"hiring_countries":[],"hiring_countries_total":0,"salary":{"min":70700,"max":112900,"currency":"CAD","period":"year","gross":null,"usd_annual":79214},"salary_estimate":null,"experience_years_min":null,"visa_sponsorship":false,"relocation_package":false,"has_equity":true,"technologies":[{"name":"Python","optional":true}],"status":"closed","first_seen_at":"2026-08-27T00:00:00Z","employer_posted_date":"2026-08-27","last_verified_at":"2026-10-25T03:00:29Z","board_verified":false,"closed_at":"2026-10-25T03:00:29Z","days_open":59,"trust":{"level":"not_scored","repost_count":null,"flags":[],"days_open":59},"description":"As the global leader in high-speed connectivity, Ciena builds the critical infrastructure powering the AI era. We’re a technology company shaping the future of networking, guided by innovation, integrity, and collaboration. Through development opportunities, meaningful work, and flexibility, Ciena supports growth and well-being-on and off the job. Connect with a career that matters.\nThe Wavelogic family of products are widely used in Ciena's optical fiber transmission solutions and are one of the main contributors to Ciena's success in the telecommunications industry. This role offers the opportunity to shape the front-end implementation of industry leading ASIC technology and contribute to the methodologies that keep Ciena at the forefront of high-performance optical networking.\nHow you will make an impact:\nExecute frontend implementation for assigned IP subsystems, including synthesis, static timing analysis, logical equivalence checking, and clock domain crossing validation\n\nDevelop and maintain timing constraints to support synthesis and signoff for subsystem integration\n\nPerform logical equivalence verification between Register Transfer Level (RTL) and gatelevel netlists throughout preand postlayout stages\n\nValidate clock domain crossings for toplevel ASIC integration to ensure functional integrity\n\nCreate and optimize scripts, tools, and documentation that improve synthesis and static timing workflows\n\nImplement engineering change orders (ECOs) to support iterative design refinement\n\nCollaborate closely with ASIC integration, IP development, physical design, and external Electronic Design Automation (EDA) partners to align frontend and backend implementation activities\n\nThe must haves:\nB.Sc. in Electrical Engineering, Computer Engineering, or a related discipline (or equivalent experience)\n\nKnowledge of ASIC implementation flows, including synthesis, timing analysis, logical equivalence checking, and clock domain crossing validation\n\nFamiliarity with RTL design principles and hardware description languages\n\nAbility to work effectively within multidisciplinary engineering teams and manage deliverables to project schedules\n\nNice to haves:\nExperience with additional frontend or backend design activities such asfloorplanning, Design for Testability (DFT), or place and route\n\nIndustry experience using synthesis and/or static timing analysis tools within an ASIC development environment\n\nHandson exposure to deepsubmicron ASIC technologies and advanced timing closure methodologies\n\nScripting experience (e.g., Python,Tcl, or similar) to enhance automation and debug workflows\n\nBackground supporting DSPcentric or highspeed ASIC development programs\n\nExperience working with external EDA vendors or foundry technology teams\n\nPay Range:\nThe annual salary range for this position is $70,700 - $112,900\nPay ranges at Ciena are designed to accommodate variations in knowledge, skills, experience, market conditions, and locations, reflecting our diverse products, industries, and lines of business. Please note that the pay range information provided in this posting pertains specifically to the primary location, which is the top location listed in case multiple locations are available.\nNon-Sales employees may be eligible for a discretionary incentive bonus, while Sales employees may be eligible for a sales commission. In addition to competitive compensation, Ciena offers a comprehensive benefits package, including medical, dental, and vision plans, participation in 401(K) (USA) & DCPP (Canada) with company matching, Employee Stock Purchase Program (ESPP), Employee Assistance Program (EAP), company-paid holidays, paid sick leave, and vacation time. We also comply with all applicable laws regarding Paid Family Leave and other leaves of absence.\nAt Ciena, we are committed to building and fostering an environment in which our employees feel respected, valued, and heard. Ciena values the diversity of its workforce and respects its employees as individuals. We do not tolerate any form of discrimination.\nCiena is an Equal Opportunity Employer, including disability and protected veteran status.\nIf contacted in relation to a job opportunity, please advise Ciena of any accommodation measures you may require.","description_format":"text","description_chars":4259,"description_truncated":false,"requirements":{"experience_years_min":null,"management_years_min":null,"team_size_min":null,"manages_managers":false,"education":{"level":"bachelor","optional":false},"security_clearance":false,"languages":[]},"benefits":["Parental leave"],"hiring_locations":[],"hiring_excludes":[],"relocation_offered":false,"industries":["Telecom Infrastructure","Optical Communications"],"lifecycle":[{"event":"open","at":"2026-10-10T16:58:59Z"},{"event":"close","at":"2026-10-25T03:00:29Z"}],"visa":[{"country":"CA","licensed_sponsor":true,"evidence":"Positions approved through LMIA in 12 months: 5","filings_12m":5,"filings_prev_12m":2,"green_card_filings_12m":null,"median_offered_wage_usd":null,"route":"Global Talent Stream; High Wage","cap_exempt":false,"checked_at":"2026-10-03T21:10:52+00:00","sources":["ESDC: employers issued a positive LMIA"],"filings_for_role_12m":2}],"liveness":null,"pay":{"stated_usd_annual":79214,"is_top_pay":false},"html_url":"https://alion.io/job/ciena-asic-synthesis-and-sta-engineer-new-grad","json_url":"https://alion.io/job/ciena-asic-synthesis-and-sta-engineer-new-grad.json","meta":{"generated_at":"2026-10-25T14:43:01Z","cache_seconds":300,"methodology":"https://alion.io/methodology","terms":"https://alion.io/terms","contact":"https://alion.io/contact","api":"https://alion.io/developers","about":"Alion is a live layer of people, companies and AI agents: who they are, whether they are real and active right now, what they do and how to work with them, readable by people and by agents and paid per call.","catalog":"https://alion.io/catalog.json","usage":{"tier":"crawler_verified","counted_by":"address","units_charged":1,"used_today":21219,"day_limit":null,"remaining_today":null,"minute_limit":300,"resets_at":"2026-10-26T00:00:00Z"}},"offers":[{"id":"company.slices","title":"One company in depth, by slice","status":"live","price":{"credits":0.02,"usd":0.002,"plus_per_slice":{"credits":0.05,"usd":0.005}},"unit":"per company, plus each slice with data","note":"the employer in depth","call":{"mcp_tool":"get_company","arguments":{"id":1996},"rest":"https://alion.io/mcp/rest/get_company?id=1996"},"human":"https://alion.io/catalog?offer=company.slices&for=job%2Fciena-asic-synthesis-and-sta-engineer-new-grad"},{"id":"market.stats","title":"A market slice: pay, demand and time to fill","status":"live","price":{"credits":1,"usd":0.1},"unit":"per slice","note":"pay, demand and time to fill for this role and place","call":{"mcp_tool":"market_stats"},"human":"https://alion.io/catalog?offer=market.stats&for=job%2Fciena-asic-synthesis-and-sta-engineer-new-grad"},{"id":"job.search","title":"Open jobs by role, technology, place, pay and visa","status":"live","price":{"credits":0.02,"usd":0.002},"unit":"per posting in a list","note":"similar open postings","call":{"mcp_tool":"search_jobs"},"human":"https://alion.io/catalog?offer=job.search&for=job%2Fciena-asic-synthesis-and-sta-engineer-new-grad"},{"id":"company.verify","title":"Is this company real and active right now","status":"pilot","price":null,"unit":"per company","request":{"url":"https://alion.io/catalog/request","method":"POST","body":"{\"offer\": \"company.verify\", \"for\": \"job/ciena-asic-synthesis-and-sta-engineer-new-grad\", \"note\": \"what you need it for\"}"},"human":"https://alion.io/catalog?offer=company.verify&for=job%2Fciena-asic-synthesis-and-sta-engineer-new-grad"}]}