{"id":2227792,"url":"https://alion.io/job/ciena-asicfpga-design-engineer","title":"ASIC/FPGA Design Engineer","company":{"id":1996,"name":"Ciena Corporation","domain":"ciena.com","url":"https://alion.io/company/ciena","size_band":"1001-5000","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Workday","truth_index":{"grade":"B","score":80,"open_postings":24,"ghost_share":0,"stale_share":1,"repost_share":0,"time_to_fill_p50_days":10,"computed_at":"2026-10-12T06:55:09Z"}},"role":"Hardware","role_family":"Hardware","seniority":"staff","employment_type":"full_time","work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Gurgaon, India"],"countries":["IN"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":{"min_usd":27000,"max_usd":56000,"period":"year","method":"global_role_cell_scaled_by_country","sample_n":539},"experience_years_min":10,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"SystemVerilog","optional":false},{"name":"Verilog","optional":false},{"name":"Xilinx Vivado","optional":false},{"name":"Perl","optional":true},{"name":"Python","optional":true}],"status":"live","first_seen_at":"2026-09-03T00:00:00Z","employer_posted_date":"2026-09-03","last_verified_at":"2026-10-12T06:07:14Z","board_verified":true,"closed_at":null,"days_open":39,"trust":{"level":"ok","repost_count":null,"flags":[],"days_open":39},"description":"As the global leader in high-speed connectivity, Ciena is committed to a people-first approach. Our teams enjoy a culture focused on prioritizing a flexible work environment that empowers individual growth, well-being, and belonging. We’re a technology company that leads with our humanity-driving our business priorities alongside meaningful social, community, and societal impact.\nCiena India Private Limited seeks an ASIC/FPGA Design Engineer to contribute to the design, verification, and implementation of networking hardware. The role supports FPGA designs across data path and control functions and contributes throughout the product development lifecycle. Success in this position helps deliver reliable, high-performance networking solutions.\nHow you will make an impact:\nDesign, develop, and verify digital logic for ASICs and FPGAs using Verilog and SystemVerilog.\n\nContribute to VLSI design activities from specification through synthesis, place and route, and timing closure.\n\nPerform logic simulation and analyze results to validate functional correctness and performance.\n\nCollaborate on hardware-software integration to enable system operation.\n\nExecute design bring-up, debugging, and validation activities in the lab.\n\nInvestigate customer issues and deliver resolutions.\n\nMentor new graduates and junior team members.\n\nThe must haves:\nEducation: Master’s degree in Electrical Engineering OR Bachelor’s degree in Electrical Engineering, Computer Engineering, or a related field.\n\nExperience: 10+ years of progressive engineering experience, ideally within a product development company.\n\nApplication of ASIC and FPGA design methodologies.\n\nUtilization of Verilog and SystemVerilog for digital design and verification.\n\nExperience with IP integration and hardware-software integration.\n\nKnowledge of transport system design and protocols including Ethernet and OTN, and interface protocols such as PCIe, SPI, I2C, and MDIO.\n\nApplication of back-end constraints and entry into vendor design flows.\n\nUtilization of design tools such as Vivado and Quartus.\n\nProblem-solving, analytical, and independent thinking applied to design challenges.\n\nCommunication and collaboration skills used in cross-functional environments.\n\nNice to haves:\nScripting knowledge using Tcl, Python, or Perl.\n\nAt Ciena, we are committed to building and fostering an environment in which our employees feel respected, valued, and heard. Ciena values the diversity of its workforce and respects its employees as individuals. We do not tolerate any form of discrimination.\nCiena is an Equal Opportunity Employer, including disability and protected veteran status.\nIf contacted in relation to a job opportunity, please advise Ciena of any accommodation measures you may require.","description_format":"text","description_chars":2764,"description_truncated":false,"requirements":{"experience_years_min":10,"management_years_min":null,"team_size_min":null,"manages_managers":false,"education":{"level":"bachelor","optional":false},"security_clearance":false,"languages":[]},"benefits":["Flexible schedule"],"hiring_locations":[],"hiring_excludes":[],"relocation_offered":false,"industries":["Telecom Infrastructure","Optical Communications"],"lifecycle":[{"event":"open","at":"2026-10-10T16:58:59Z"}],"visa":[],"liveness":{"score":12,"band":"cold","label":"Long shot","p_open":1,"p_active":0.342,"p_room":0.35,"age_days":39,"expected_fill_days":10,"reasons":["conf:0","stale_co","win:tail","comp:brand"],"computed_at":"2026-10-12T06:55:09Z"},"pay":null,"html_url":"https://alion.io/job/ciena-asicfpga-design-engineer","json_url":"https://alion.io/job/ciena-asicfpga-design-engineer.json","meta":{"generated_at":"2026-10-12T13:08:52Z","cache_seconds":300,"methodology":"https://alion.io/methodology","terms":"https://alion.io/terms","contact":"https://alion.io/contact","api":"https://alion.io/developers","about":"Alion is a live layer of people, companies and AI agents: who they are, whether they are real and active right now, what they do and how to work with them, readable by people and by agents and paid per call.","catalog":"https://alion.io/catalog.json","usage":{"tier":"crawler_verified","counted_by":"address","units_charged":1,"used_today":20556,"day_limit":null,"remaining_today":null,"minute_limit":300,"resets_at":"2026-10-13T00:00:00Z"}},"offers":[{"id":"company.slices","title":"One company in depth, by slice","status":"live","price":{"credits":0.02,"usd":0.002,"plus_per_slice":{"credits":0.05,"usd":0.005}},"unit":"per company, plus each slice with data","note":"the employer in depth","call":{"mcp_tool":"get_company","arguments":{"id":1996},"rest":"https://alion.io/mcp/rest/get_company?id=1996"},"human":"https://alion.io/catalog?offer=company.slices&for=job%2Fciena-asicfpga-design-engineer"},{"id":"market.stats","title":"A market slice: pay, demand and time to fill","status":"live","price":{"credits":1,"usd":0.1},"unit":"per slice","note":"pay, demand and time to fill for this role and place","call":{"mcp_tool":"market_stats"},"human":"https://alion.io/catalog?offer=market.stats&for=job%2Fciena-asicfpga-design-engineer"},{"id":"job.search","title":"Open jobs by role, technology, place, pay and visa","status":"live","price":{"credits":0.02,"usd":0.002},"unit":"per posting in a list","note":"similar open postings","call":{"mcp_tool":"search_jobs"},"human":"https://alion.io/catalog?offer=job.search&for=job%2Fciena-asicfpga-design-engineer"},{"id":"company.verify","title":"Is this company real and active right now","status":"pilot","price":null,"unit":"per company","request":{"url":"https://alion.io/catalog/request","method":"POST","body":"{\"offer\": \"company.verify\", \"for\": \"job/ciena-asicfpga-design-engineer\", \"note\": \"what you need it for\"}"},"human":"https://alion.io/catalog?offer=company.verify&for=job%2Fciena-asicfpga-design-engineer"}]}