{"id":3551652,"url":"https://alion.io/job/ciena-corporation-asic-engineer-intern","title":"ASIC Engineer Intern","company":{"id":1996,"name":"Ciena Corporation","domain":"ciena.com","url":"https://alion.io/company/ciena","size_band":"1001-5000","is_staffing_agency":false,"employer_type":"direct","is_intermediary":false,"listed_via":null,"ats_vendor":"Workday","truth_index":{"grade":"B","score":79,"open_postings":29,"ghost_share":0,"stale_share":0.828,"repost_share":0.034,"time_to_fill_p50_days":30,"computed_at":"2026-11-08T05:47:12Z"}},"role":"Hardware","role_family":"Hardware","seniority":"intern","employment_type":"internship","work_mode":"on_site","remote_scope":null,"remote_scope_basis":null,"remote_working_hours":null,"hiring_geo_confidence":"structured","locations":["Ottawa, Canada"],"countries":["CA"],"hiring_countries":[],"hiring_countries_total":0,"salary":null,"salary_estimate":null,"experience_years_min":null,"visa_sponsorship":false,"relocation_package":false,"has_equity":false,"technologies":[{"name":"Java","optional":false},{"name":"Linux","optional":false},{"name":"Python","optional":false},{"name":"SystemVerilog","optional":false},{"name":"UVM","optional":false},{"name":"Agile","optional":true},{"name":"Confluence","optional":true},{"name":"Git","optional":true}],"status":"live","first_seen_at":"2026-10-30T22:57:53Z","employer_posted_date":"2026-10-30","last_verified_at":"2026-11-07T04:49:18Z","board_verified":true,"closed_at":null,"days_open":8,"trust":{"level":"ok","repost_count":null,"flags":[],"days_open":8},"description":"As the global leader in high-speed connectivity, Ciena builds the critical infrastructure powering the AI era. We’re a technology company shaping the future of networking, guided by innovation, integrity, and collaboration. Through development opportunities, meaningful work, and flexibility, Ciena supports growth and well-being-on and off the job. Connect with a career that matters.\nThe Opportunity: Work term of 4 months extendable to 8, starting in January 2027.\nCiena is seeking a student to contribute to the development and evolution of automation infrastructure used for next-generation ASIC devices. The role provides exposure to ASIC design, integration, layout, and verification activities within large-scale DSP ASIC development for optical communications. The position is aligned to a student’s experience, strengths, and technical interests.\nHow you will make an impact:\nContribute to the development of automation infrastructure for ASIC devices.\nCollaborate with developers and team leads to advance ASIC design, layout, integration, and verification activities.\nDevelop design blocks and evaluate designs for correctness and performance.\nImplement netlists into silicon-realizable layouts and automate placement and extraction workflows.\nCreate constraints, analyze implementation reports, and automate ASIC integration processes.\nDevelop reusable SystemVerilog/UVM verification components.\nEnhance Python-based reporting, analysis, build, simulation, and debug workflows.\nThe must haves:\nProgramming experience using one or more of Java, Python, TCL, Skill/Ocean, or SystemVerilog.\nFamiliarity with Linux-based development environments.\nNice to haves:\nPrevious experience with ASIC or FPGA development programs.\nStrong analytical and debugging skills.\nFamiliarity with Agile, JIRA, Confluence, and Git.\nPay Range:\nThe hourly pay range for this position is $25.50 - $35.00.\nPay ranges at Ciena are designed to accommodate variations in knowledge, skills, experience, market conditions, and locations, reflecting our diverse products, industries, and lines of business. Please note that the pay range information provided in this posting pertains specifically to the primary location, which is the top location listed in case multiple locations are available.\nIn addition to competitive compensation, Ciena offers students access to the Employee Assistance Program (EAP), company-paid holidays, paid sick leave, and vacation pay as required by applicable laws.\nAt Ciena, we are committed to building and fostering an environment in which our employees feel respected, valued, and heard. Ciena values the diversity of its workforce and respects its employees as individuals. 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